Lines Matching refs:STORE
702 a load or store instruction is not aligned on a four byte boundary,
705 align load and store instructions on four byte boundaries if we
1004 /* Look for load and store instructions that we can align on four
1550 #define STORE (0x2)
1656 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1657 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1658 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1675 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1685 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1686 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1687 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1688 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1689 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1690 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1734 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
1744 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
1754 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
1762 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1765 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */
1768 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */
1771 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */
1774 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */
1777 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */
1780 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */
1787 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */
1848 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1849 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
1899 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
1900 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
1901 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
1912 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
1913 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
1914 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
1951 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
1954 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
1955 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
2006 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */
2008 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */
2010 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */
2012 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
2355 || (op->flags & (LOAD | STORE)) == 0)
2358 /* This is a load or store which is not on a four byte boundary. */
2367 a load / store after all. Note that the test here might mistake
2389 /* If the load/store instruction is in a delay slot, we
2398 && (prev_op->flags & (LOAD | STORE)) == 0
2403 /* The load/store instruction does not have a label, and
2405 itself a load/store instruction, and PREV_INSN and
2454 /* There is an instruction after the load/store
2459 && (next_op->flags & (LOAD | STORE)) == 0
2464 /* NEXT_INSN is not itself a load/store instruction,
2482 after NEXT_INSN is itself a load or store
2497 || ((next2_op->flags & (LOAD | STORE)) == 0
Indexes created Sun Jun 28 00:24:58 UTC 2026