Lines Matching refs:SELID
64 static const char * selid_out_of_range = N_ ("SelID is out of range");
68 static const char * sr_selid_out_of_range = N_ ("SR/SelID is out of range");
689 insert_SELID (unsigned long insn, unsigned long selid, const char ** errmsg)
691 if (selid > 0x1f)
694 return insn | ((selid & 0x1fUL) << 27);
700 unsigned long selid;
705 selid = ((insn2 & 0xf800) >> 11);
710 return selid;
884 unsigned long sr,selid;
890 selid = (imm10 & 0x3e0) >> 5;
893 ret = insn | selid << 27 | sr;
902 unsigned long sr, selid;
907 selid = ((insn2 & 0xf800) >> 11);
910 ret = (selid << 5) | sr;
922 unsigned long sr, selid;
928 selid = (imm10 & 0x3e0) >> 5;
931 ret = insn | selid << 27 | sr << 11;
940 unsigned long sr, selid;
945 selid = ((insn2 & 0xf800) >> 11);
948 ret = (selid << 5) | sr;
1253 #define SELID (WIDTH_L + 1)
1256 #define RIE_IMM5 (SELID + 1)
1599 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1604 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1610 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1755 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1760 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1765 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP },
Indexes created Sun Jun 28 00:24:58 UTC 2026