Cross Reference: /src/external/gpl3/gdb/dist/sim/aarch64/cpustate.c

Lines Matching refs:ELEMENT
459 #define GET_VEC_ELEMENT(REG, ELEMENT, FIELD)				\
464       if (ELEMENT >= ARRAY_SIZE (aarch64_cpu->fr[0].FIELD))		\
467 			  "Internal SIM error: invalid element number: %d ",\
468 			  ELEMENT);					\
472       return aarch64_cpu->fr[REG].FIELD [ELEMENT];			\
477 aarch64_get_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element)
479   GET_VEC_ELEMENT (reg, element, v);
483 aarch64_get_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element)
485   GET_VEC_ELEMENT (reg, element, w);
489 aarch64_get_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element)
491   GET_VEC_ELEMENT (reg, element, h);
495 aarch64_get_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element)
497   GET_VEC_ELEMENT (reg, element, b);
501 aarch64_get_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element)
503   GET_VEC_ELEMENT (reg, element, V);
507 aarch64_get_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element)
509   GET_VEC_ELEMENT (reg, element, W);
513 aarch64_get_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element)
515   GET_VEC_ELEMENT (reg, element, H);
519 aarch64_get_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element)
521   GET_VEC_ELEMENT (reg, element, B);
525 aarch64_get_vec_float (sim_cpu *cpu, VReg reg, unsigned element)
527   GET_VEC_ELEMENT (reg, element, S);
531 aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element)
533   GET_VEC_ELEMENT (reg, element, D);
537 #define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER)		\
542       if (ELEMENT >= ARRAY_SIZE (aarch64_cpu->fr[0].FIELD))		\
545 			  "Internal SIM error: invalid element number: %d ",\
546 			  ELEMENT);					\
550       if (VAL != aarch64_cpu->fr[REG].FIELD [ELEMENT])			\
554 			ELEMENT, aarch64_cpu->fr[REG].FIELD [ELEMENT], VAL); \
556       aarch64_cpu->fr[REG].FIELD [ELEMENT] = VAL;				\
561 aarch64_set_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element, uint64_t val)
563   SET_VEC_ELEMENT (reg, element, val, v, "%16" PRIx64);
567 aarch64_set_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element, uint32_t val)
569   SET_VEC_ELEMENT (reg, element, val, w, "%8x");
573 aarch64_set_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element, uint16_t val)
575   SET_VEC_ELEMENT (reg, element, val, h, "%4x");
579 aarch64_set_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element, uint8_t val)
581   SET_VEC_ELEMENT (reg, element, val, b, "%x");
585 aarch64_set_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element, int64_t val)
587   SET_VEC_ELEMENT (reg, element, val, V, "%16" PRIx64);
591 aarch64_set_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element, int32_t val)
593   SET_VEC_ELEMENT (reg, element, val, W, "%8x");
597 aarch64_set_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element, int16_t val)
599   SET_VEC_ELEMENT (reg, element, val, H, "%4x");
603 aarch64_set_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element, int8_t val)
605   SET_VEC_ELEMENT (reg, element, val, B, "%x");
609 aarch64_set_vec_float (sim_cpu *cpu, VReg reg, unsigned element, float val)
611   SET_VEC_ELEMENT (reg, element, val, S, "%f");
615 aarch64_set_vec_double (sim_cpu *cpu, VReg reg, unsigned element, double val)
617   SET_VEC_ELEMENT (reg, element, val, D, "%f");
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