Cross Reference: /src/external/gpl3/gdb/dist/sim/arm/maverick.c

Lines Matching refs:lower
87       /* Move lower half of a DF stored in a DSP reg into an Arm reg.  */
89       printfdbg ("\tlower half=0x%x\n", DSPregs[SRC1_REG].lower.i);
92       *value = (ARMword) DSPregs[SRC1_REG].lower.i;
208       /* Move lower half of 64bit int from Cirrus to Arm.  */
209       *value = (ARMword) DSPregs[SRC1_REG].lower.i;
232 	a = DSPregs[SRC1_REG].lower.i;
233 	b = DSPregs[SRC2_REG].lower.i;
235 	res = DSPregs[SRC1_REG].lower.i - DSPregs[SRC2_REG].lower.i;
241 	v = SubOverflow (DSPregs[SRC1_REG].lower.i, DSPregs[SRC2_REG].lower.i,
343       /* Move the lower half of a DF value from an Arm register into
344 	 the lower half of a Cirrus register.  */
346       DSPregs[SRC1_REG].lower.i = (int) value;
386       /* Move lower half of a 64bit int from an ARM register into the
387          lower half of a DSP register and sign extend it.  */
389       DSPregs[SRC1_REG].lower.i = (int) value;
405 	DSPregs[SRC2_REG].lower.i = DSPregs[SRC1_REG].lower.i << value;
407 	DSPregs[SRC2_REG].lower.i = DSPregs[SRC1_REG].lower.i >> -value;
495 	    DSPregs[DEST_REG].lower.i = (int) data;
500 	    DSPregs[DEST_REG].lower.i = (int) data;
559 	    DSPregs[DEST_REG].lower.i = (int) data;
564 	    DSPregs[DEST_REG].lower.i = (int) data;
620 	    *data = (ARMword) DSPregs[DEST_REG].lower.i;
625 	    *data = (ARMword) DSPregs[DEST_REG].lower.i;
680 	    *data = (ARMword) DSPregs[DEST_REG].lower.i;
685 	    *data = (ARMword) DSPregs[DEST_REG].lower.i;
706       *data = (ARMword) DSPregs[DEST_REG].lower.i;
764 		     (float) DSPregs[SRC1_REG].lower.i);
765 	  DSPregs[DEST_REG].upper.f = (float) DSPregs[SRC1_REG].lower.i;
772 		     (double) DSPregs[SRC1_REG].lower.i);
773 	  mv_setRegDouble (DEST_REG, (double) DSPregs[SRC1_REG].lower.i);
941 	 DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i >> -shift;
944 	 DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i << shift;
951 	   DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i
952 	     * DSPregs[SRC2_REG].lower.i;
957 		      DSPregs[DEST_REG].lower.i);
972 	   DSPregs[DEST_REG].lower.i
973 	     += DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i;
978 		      DSPregs[DEST_REG].lower.i);
982 	   DSPregs[DEST_REG].lower.i
983 	     -= DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i;
988 		      DSPregs[DEST_REG].lower.i);
993 	   DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f;
997 		      DSPregs[DEST_REG].lower.i);
1002 	   DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG);
1006 		      DSPregs[DEST_REG].lower.i);
1010 	   DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f;
1014 		      DSPregs[DEST_REG].lower.i);
1018 	   DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG);
1022 		      DSPregs[DEST_REG].lower.i);
1046 	   DSPregs[DEST_REG].lower.i = (DSPregs[SRC1_REG].lower.i < 0
1047 	     ? -DSPregs[SRC1_REG].lower.i : DSPregs[SRC1_REG].lower.i);
1052 		      DSPregs[DEST_REG].lower.i);
1068 	   DSPregs[DEST_REG].lower.i = -DSPregs[SRC1_REG].lower.i;
1073 		      DSPregs[DEST_REG].lower.i);
1086 	   DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i
1087 	     + DSPregs[SRC2_REG].lower.i;
1092 		      DSPregs[DEST_REG].lower.i);
1107 	   DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i
1108 	     - DSPregs[SRC2_REG].lower.i;
1113 		      DSPregs[DEST_REG].lower.i);
1174    32-bit integers are stored in the LOWER half of a 64-bit physical
1184   reg_conv.ints[msw_float_index] = DSPregs[regnum].lower.i;
1193   DSPregs[regnum].lower.i = reg_conv.ints[msw_float_index];
1199   reg_conv.ints[lsw_int_index] = DSPregs[regnum].lower.i;
1208   DSPregs[regnum].lower.i = reg_conv.ints[lsw_int_index];
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