Lines Matching defs:pll
1 /* Blackfin Phase Lock Loop (PLL) model.
55 struct bfin_pll *pll = hw_data (me);
70 mmr_off = addr - pll->base;
71 valuep = (void *)((uintptr_t)pll + mmr_base() + mmr_off);
98 struct bfin_pll *pll = hw_data (me);
108 mmr_off = addr - pll->base;
109 valuep = (void *)((uintptr_t)pll + mmr_base() + mmr_off);
132 { "pll", 0, 0, output_port, },
137 attach_bfin_pll_regs (struct hw *me, struct bfin_pll *pll)
161 pll->base = attach_address;
167 struct bfin_pll *pll;
169 pll = HW_ZALLOC (me, struct bfin_pll);
171 set_hw_data (me, pll);
176 attach_bfin_pll_regs (me, pll);
178 /* Initialize the PLL. */
180 pll->pll_ctl = 0x1400;
181 pll->pll_div = 0x0005;
182 pll->vr_ctl = 0x40DB;
183 pll->pll_stat = 0x00A2;
184 pll->pll_lockcnt = 0x0200;
185 pll->chipid = bfin_model_get_chipid (hw_system (me));
188 pll->pll_ctl = 0xa800;
189 pll->pll_div = 0x4;
190 pll->vr_ctl = 0x40fb;
191 pll->pll_stat = 0xa2;
192 pll->pll_lockcnt = 0x300;
Indexes created Sat Apr 25 00:22:52 UTC 2026