Lines Matching defs:sic
1 /* Blackfin System Interrupt Controller (SIC) model.
137 bfin_sic_52x_forward_interrupts (struct hw *me, struct bfin_sic *sic)
139 bfin_sic_forward_interrupts (me, &sic->bf52x.isr0, &sic->bf52x.imask0, &sic->bf52x.iar0);
140 bfin_sic_forward_interrupts (me, &sic->bf52x.isr1, &sic->bf52x.imask1, &sic->bf52x.iar4);
147 struct bfin_sic *sic = hw_data (me);
162 mmr_off = addr - sic->base;
163 valuep = (void *)((uintptr_t)sic + mmr_base() + mmr_off);
168 /* XXX: Discard all SIC writes for now. */
179 bfin_sic_52x_forward_interrupts (me, sic);
204 struct bfin_sic *sic = hw_data (me);
214 mmr_off = addr - sic->base;
215 valuep = (void *)((uintptr_t)sic + mmr_base() + mmr_off);
250 bfin_sic_537_forward_interrupts (struct hw *me, struct bfin_sic *sic)
252 bfin_sic_forward_interrupts (me, &sic->bf537.isr, &sic->bf537.imask, &sic->bf537.iar0);
259 struct bfin_sic *sic = hw_data (me);
274 mmr_off = addr - sic->base;
275 valuep = (void *)((uintptr_t)sic + mmr_base() + mmr_off);
280 /* XXX: Discard all SIC writes for now. */
290 bfin_sic_537_forward_interrupts (me, sic);
315 struct bfin_sic *sic = hw_data (me);
325 mmr_off = addr - sic->base;
326 valuep = (void *)((uintptr_t)sic + mmr_base() + mmr_off);
360 bfin_sic_54x_forward_interrupts (struct hw *me, struct bfin_sic *sic)
362 bfin_sic_forward_interrupts (me, &sic->bf54x.isr0, &sic->bf54x.imask0, &sic->bf54x.iar0);
363 bfin_sic_forward_interrupts (me, &sic->bf54x.isr1, &sic->bf54x.imask1, &sic->bf54x.iar4);
364 bfin_sic_forward_interrupts (me, &sic->bf54x.isr2, &sic->bf54x.imask2, &sic->bf54x.iar8);
371 struct bfin_sic *sic = hw_data (me);
386 mmr_off = addr - sic->base;
387 valuep = (void *)((uintptr_t)sic + mmr_base() + mmr_off);
392 /* XXX: Discard all SIC writes for now. */
402 bfin_sic_54x_forward_interrupts (me, sic);
424 struct bfin_sic *sic = hw_data (me);
434 mmr_off = addr - sic->base;
435 valuep = (void *)((uintptr_t)sic + mmr_base() + mmr_off);
466 bfin_sic_561_forward_interrupts (struct hw *me, struct bfin_sic *sic)
468 bfin_sic_forward_interrupts (me, &sic->bf561.isr0, &sic->bf561.imask0, &sic->bf561.iar0);
469 bfin_sic_forward_interrupts (me, &sic->bf561.isr1, &sic->bf561.imask1, &sic->bf561.iar4);
476 struct bfin_sic *sic = hw_data (me);
491 mmr_off = addr - sic->base;
492 valuep = (void *)((uintptr_t)sic + mmr_base() + mmr_off);
497 /* XXX: Discard all SIC writes for now. */
508 bfin_sic_561_forward_interrupts (me, sic);
533 struct bfin_sic *sic = hw_data (me);
543 mmr_off = addr - sic->base;
544 valuep = (void *)((uintptr_t)sic + mmr_base() + mmr_off);
578 /* Give each SIC its own base to make it easier to extract the pin at
579 runtime. The pin is used as its bit position in the SIC MMRs. */
580 #define ENC(sic, pin) (((sic) << 8) + (pin))
681 struct bfin_sic *sic = hw_data (me);
686 HW_TRACE ((me, "processing level %i from port %i (SIC %u pin %u)",
689 /* SIC only exists to forward interrupts from the system to the CEC. */
692 case 0: bfin_sic_port_event (me, &sic->bf52x.isr0, bit, level); break;
693 case 1: bfin_sic_port_event (me, &sic->bf52x.isr1, bit, level); break;
696 /* XXX: Handle SIC wakeup source ?
697 if (sic->bf52x.iwr0 & bit)
699 if (sic->bf52x.iwr1 & bit)
703 bfin_sic_52x_forward_interrupts (me, sic);
710 struct bfin_sic *sic = hw_data (me);
715 HW_TRACE ((me, "processing level %i from port %i (SIC %u pin %u)",
718 /* SIC only exists to forward interrupts from the system to the CEC. */
719 bfin_sic_port_event (me, &sic->bf537.isr, bit, level);
721 /* XXX: Handle SIC wakeup source ?
722 if (sic->bf537.iwr & bit)
726 bfin_sic_537_forward_interrupts (me, sic);
733 struct bfin_sic *sic = hw_data (me);
738 HW_TRACE ((me, "processing level %i from port %i (SIC %u pin %u)",
741 /* SIC only exists to forward interrupts from the system to the CEC. */
744 case 0: bfin_sic_port_event (me, &sic->bf54x.isr0, bit, level); break;
745 case 1: bfin_sic_port_event (me, &sic->bf54x.isr0, bit, level); break;
746 case 2: bfin_sic_port_event (me, &sic->bf54x.isr0, bit, level); break;
749 /* XXX: Handle SIC wakeup source ?
750 if (sic->bf54x.iwr0 & bit)
752 if (sic->bf54x.iwr1 & bit)
754 if (sic->bf54x.iwr2 & bit)
758 bfin_sic_54x_forward_interrupts (me, sic);
765 struct bfin_sic *sic = hw_data (me);
770 HW_TRACE ((me, "processing level %i from port %i (SIC %u pin %u)",
773 /* SIC only exists to forward interrupts from the system to the CEC. */
776 case 0: bfin_sic_port_event (me, &sic->bf561.isr0, bit, level); break;
777 case 1: bfin_sic_port_event (me, &sic->bf561.isr1, bit, level); break;
780 /* XXX: Handle SIC wakeup source ?
781 if (sic->bf561.iwr0 & bit)
783 if (sic->bf561.iwr1 & bit)
787 bfin_sic_561_forward_interrupts (me, sic);
791 attach_bfin_sic_regs (struct hw *me, struct bfin_sic *sic)
815 sic->base = attach_address;
821 struct bfin_sic *sic;
823 sic = HW_ZALLOC (me, struct bfin_sic);
825 set_hw_data (me, sic);
826 attach_bfin_sic_regs (me, sic);
837 /* Initialize the SIC. */
838 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
839 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
840 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
841 sic->bf52x.iar0 = 0x00000000;
842 sic->bf52x.iar1 = 0x22111000;
843 sic->bf52x.iar2 = 0x33332222;
844 sic->bf52x.iar3 = 0x44444433;
845 sic->bf52x.iar4 = 0x55555555;
846 sic->bf52x.iar5 = 0x06666655;
847 sic->bf52x.iar6 = 0x33333003;
848 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
857 /* Initialize the SIC. */
858 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
859 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
860 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
861 sic->bf52x.iar0 = 0x00000000;
862 sic->bf52x.iar1 = 0x11000000;
863 sic->bf52x.iar2 = 0x33332222;
864 sic->bf52x.iar3 = 0x44444433;
865 sic->bf52x.iar4 = 0x55555555;
866 sic->bf52x.iar5 = 0x06666655;
867 sic->bf52x.iar6 = 0x33333000;
868 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
877 /* Initialize the SIC. */
878 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
879 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
880 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
881 sic->bf52x.iar0 = 0x00000000;
882 sic->bf52x.iar1 = 0x11000000;
883 sic->bf52x.iar2 = 0x33332222;
884 sic->bf52x.iar3 = 0x44444433;
885 sic->bf52x.iar4 = 0x55555555;
886 sic->bf52x.iar5 = 0x06666655;
887 sic->bf52x.iar6 = 0x33333000;
888 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
897 /* Initialize the SIC. */
898 sic->bf537.imask = 0;
899 sic->bf537.isr = 0;
900 sic->bf537.iwr = 0xFFFFFFFF;
901 sic->bf537.iar0 = 0x10000000;
902 sic->bf537.iar1 = 0x33322221;
903 sic->bf537.iar2 = 0x66655444;
904 sic->bf537.iar3 = 0; /* XXX: fix this */
915 /* Initialize the SIC. */
916 sic->bf537.imask = 0;
917 sic->bf537.isr = 0;
918 sic->bf537.iwr = 0xFFFFFFFF;
919 sic->bf537.iar0 = 0x22211000;
920 sic->bf537.iar1 = 0x43333332;
921 sic->bf537.iar2 = 0x55555444;
922 sic->bf537.iar3 = 0x66655555;
931 /* Initialize the SIC. */
932 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
933 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
934 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
935 sic->bf52x.iar0 = 0x10000000;
936 sic->bf52x.iar1 = 0x33322221;
937 sic->bf52x.iar2 = 0x66655444;
938 sic->bf52x.iar3 = 0x00000000;
939 sic->bf52x.iar4 = 0x32222220;
940 sic->bf52x.iar5 = 0x44433333;
941 sic->bf52x.iar6 = 0x00444664;
942 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
951 /* Initialize the SIC. */
952 sic->bf54x.imask0 = sic->bf54x.imask1 = sic->bf54x.imask2 = 0;
953 sic->bf54x.isr0 = sic->bf54x.isr1 = sic->bf54x.isr2 = 0;
954 sic->bf54x.iwr0 = sic->bf54x.iwr1 = sic->bf54x.iwr2 = 0xFFFFFFFF;
955 sic->bf54x.iar0 = 0x10000000;
956 sic->bf54x.iar1 = 0x33322221;
957 sic->bf54x.iar2 = 0x66655444;
958 sic->bf54x.iar3 = 0x00000000;
959 sic->bf54x.iar4 = 0x32222220;
960 sic->bf54x.iar5 = 0x44433333;
961 sic->bf54x.iar6 = 0x00444664;
962 sic->bf54x.iar7 = 0x00000000;
963 sic->bf54x.iar8 = 0x44111111;
964 sic->bf54x.iar9 = 0x44444444;
965 sic->bf54x.iar10 = 0x44444444;
966 sic->bf54x.iar11 = 0x55444444;
975 /* Initialize the SIC. */
976 sic->bf561.imask0 = sic->bf561.imask1 = 0;
977 sic->bf561.isr0 = sic->bf561.isr1 = 0;
978 sic->bf561.iwr0 = sic->bf561.iwr1 = 0xFFFFFFFF;
979 sic->bf561.iar0 = 0x00000000;
980 sic->bf561.iar1 = 0x11111000;
981 sic->bf561.iar2 = 0x21111111;
982 sic->bf561.iar3 = 0x22222222;
983 sic->bf561.iar4 = 0x33333222;
984 sic->bf561.iar5 = 0x43333333;
985 sic->bf561.iar6 = 0x21144444;
986 sic->bf561.iar7 = 0x00006552;
995 /* Initialize the SIC. */
996 sic->bf537.imask = 0;
997 sic->bf537.isr = 0;
998 sic->bf537.iwr = 0xFFFFFFFF;
999 sic->bf537.iar0 = 0x00000000;
1000 sic->bf537.iar1 = 0x33322221;
1001 sic->bf537.iar2 = 0x55444443;
1002 sic->bf537.iar3 = 0x66600005;
1005 hw_abort (me, "no support for SIC on this Blackfin model yet");
Indexes created Sun Apr 12 00:22:20 UTC 2026