Lines Matching refs:fq
327 /* Trap codes for FSR0 and FQ registers. */
533 /* SIMD instruction exception codes for FQ. */
541 /* MIV field of FQ. */
548 /* The FQ registers are 64 bits wide and are implemented as 32 bit pairs. The
554 #define SET_FQ(index, fq) \
555 (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]) = (fq))
557 #define SET_FQ_MIV(fq, miv) ( \
558 (fq) = ((fq) & ~(0x1 << 31)) | (((miv) & 0x1) << 31) \
561 #define SET_FQ_SIE(fq, sie) ( \
562 (fq) = ((fq) & ~(0x3 << 15)) | (((sie) & 0x3) << 15) \
565 #define SET_FQ_FTT(fq, ftt) ( \
566 (fq) = ((fq) & ~(0x7 << 7)) | (((ftt) & 0x7) << 7) \
569 #define SET_FQ_CEXC(fq, cexc) ( \
570 (fq) = ((fq) & ~(0x3f << 1)) | (((cexc) & 0x3f) << 1) \
573 #define GET_FQ_VALID(fq) ((fq) & 1)
574 #define SET_FQ_VALID(fq) ((fq) |= 1)
Indexes created Fri Jun 26 00:24:39 UTC 2026