Cross Reference: /src/external/gpl3/gdb/dist/sim/m32r/sem2-switch.c

Lines Matching defs:temp1
716   SI temp0;BI temp1;
718   temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
725     BI opval = temp1;
745   SI temp0;BI temp1;
747   temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
754     BI opval = temp1;
774   SI temp0;BI temp1;
776   temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
783     BI opval = temp1;
1774   SI temp0;USI temp1;
1776   temp1 = ANDSI (* FLD (i_sr), -4);
1783     USI opval = temp1;
2015   SI temp0;SI temp1;
2017   temp1 = ADDSI (* FLD (i_sr), 4);
2024     SI opval = temp1;
3024   SI temp0;BI temp1;
3026   temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
3033     BI opval = temp1;
3053   SI temp0;BI temp1;
3055   temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
3062     BI opval = temp1;
3649   SI temp0;BI temp1;
3651   temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
3658     BI opval = temp1;
3698   SI temp0;BI temp1;
3700   temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
3707     BI opval = temp1;
4293   SI temp0;USI temp1;
4295   temp1 = ANDSI (* FLD (i_sr), -4);
4302     USI opval = temp1;
4574   SI temp0;SI temp1;
4576   temp1 = ADDSI (* FLD (i_sr), 4);
4583     SI opval = temp1;
6187   SI temp0;BI temp1;
6189   temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
6196     BI opval = temp1;
6236   SI temp0;BI temp1;
6238   temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
6245     BI opval = temp1;
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