Lines Matching defs:interrupts
0 /* interrupts.c -- 68HC11 Interrupts Emulation
68 /* Serial interrupts. */
74 /* SPI interrupts. */
77 /* Realtime interrupts. */
81 /* Output compare interrupts. */
88 /* Input compare interrupts. */
116 '\0', NULL, "Print information about interrupts",
120 "Catch interrupts when they are raised or taken\n"
131 /* Initialize the interrupts module. */
135 struct interrupts *interrupts = &M68HC11_SIM_CPU (cpu)->cpu_interrupts;
137 interrupts->cpu = cpu;
142 /* Initialize the interrupts of the processor. */
144 interrupts_reset (struct interrupts *interrupts)
146 sim_cpu *cpu = interrupts->cpu;
150 interrupts->pending_mask = 0;
152 interrupts->vectors_addr = 0xbfc0;
154 interrupts->vectors_addr = 0xffc0;
155 interrupts->nb_interrupts_raised = 0;
156 interrupts->min_mask_cycles = CYCLES_MAX;
157 interrupts->max_mask_cycles = 0;
158 interrupts->last_mask_cycles = 0;
159 interrupts->start_mask_cycle = -1;
160 interrupts->xirq_start_mask_cycle = -1;
161 interrupts->xirq_max_mask_cycles = 0;
162 interrupts->xirq_min_mask_cycles = CYCLES_MAX;
163 interrupts->xirq_last_mask_cycles = 0;
167 interrupts->interrupt_order[i] = i;
171 interrupts->history_index = 0;
172 memset (interrupts->interrupts_history, 0,
173 sizeof (interrupts->interrupts_history));
175 memset (interrupts->interrupts, 0,
176 sizeof (interrupts->interrupts));
182 bfd_vma addr = interrupts->vectors_addr;
213 struct interrupts *interrupts;
218 interrupts = &M68HC11_SIM_CPU (cpu)->cpu_interrupts;
225 switch (interrupts->interrupts[id].stop_mode)
244 interrupts->interrupts[id].raised_count);
270 interrupts->interrupts[id].stop_mode = mode;
279 interrupts->interrupts[id].stop_mode = 0;
286 /* Update the mask of pending interrupts. This operation must be called
291 interrupts_update_pending (struct interrupts *interrupts)
300 ioregs = &M68HC11_SIM_CPU (interrupts->cpu)->ios[0];
332 /* Some interrupts are shared (M6811_INT_SCI) so clear
333 the interrupts before setting the new ones. */
334 interrupts->pending_mask &= ~clear_mask;
335 interrupts->pending_mask |= set_mask;
341 int64_t cycle = cpu_current_cycle (interrupts->cpu);
349 interrupts->interrupts[i].cpu_cycle = cycle;
350 if (interrupts->interrupts[i].stop_mode & SIM_STOP_WHEN_RAISED)
353 sim_io_printf (CPU_STATE (interrupts->cpu),
359 sim_engine_halt (CPU_STATE (interrupts->cpu),
360 interrupts->cpu,
361 0, cpu_get_pc (interrupts->cpu),
372 interrupts_get_current (struct interrupts *interrupts)
376 if (interrupts->pending_mask == 0)
381 if (interrupts->pending_mask & (1 << M6811_INT_SWI))
383 interrupts->pending_mask &= ~(1 << M6811_INT_SWI);
386 if (interrupts->pending_mask & (1 << M6811_INT_ILLEGAL))
388 interrupts->pending_mask &= ~(1 << M6811_INT_ILLEGAL);
394 if (interrupts->pending_mask & (1 << M6811_INT_XIRQ))
396 if (cpu_get_ccr_X (interrupts->cpu) == 0)
398 interrupts->pending_mask &= ~(1 << M6811_INT_XIRQ);
404 /* Interrupts are masked, do nothing. */
405 if (cpu_get_ccr_I (interrupts->cpu) == 1)
412 For these interrupts, the pending mask is cleared when the program
418 enum M6811_INT int_number = interrupts->interrupt_order[i];
420 if (interrupts->pending_mask & (1 << int_number))
430 be called after each instruction to handle the interrupts. If interrupts
433 interrupts_process (struct interrupts *interrupts)
438 /* See if interrupts are enabled/disabled and keep track of the
439 number of cycles the interrupts are masked. Such information is
441 ccr = cpu_get_ccr (interrupts->cpu);
444 if (interrupts->start_mask_cycle < 0)
445 interrupts->start_mask_cycle = cpu_current_cycle (interrupts->cpu);
447 else if (interrupts->start_mask_cycle >= 0
450 int64_t t = cpu_current_cycle (interrupts->cpu);
452 t -= interrupts->start_mask_cycle;
453 if (t < interrupts->min_mask_cycles)
454 interrupts->min_mask_cycles = t;
455 if (t > interrupts->max_mask_cycles)
456 interrupts->max_mask_cycles = t;
457 interrupts->start_mask_cycle = -1;
458 interrupts->last_mask_cycles = t;
462 if (interrupts->xirq_start_mask_cycle < 0)
463 interrupts->xirq_start_mask_cycle
464 = cpu_current_cycle (interrupts->cpu);
466 else if (interrupts->xirq_start_mask_cycle >= 0
469 int64_t t = cpu_current_cycle (interrupts->cpu);
471 t -= interrupts->xirq_start_mask_cycle;
472 if (t < interrupts->xirq_min_mask_cycles)
473 interrupts->xirq_min_mask_cycles = t;
474 if (t > interrupts->xirq_max_mask_cycles)
475 interrupts->xirq_max_mask_cycles = t;
476 interrupts->xirq_start_mask_cycle = -1;
477 interrupts->xirq_last_mask_cycles = t;
480 id = interrupts_get_current (interrupts);
487 if (interrupts->interrupts[id].stop_mode & SIM_STOP_WHEN_TAKEN)
489 sim_io_printf (CPU_STATE (interrupts->cpu),
492 sim_engine_halt (CPU_STATE (interrupts->cpu),
493 interrupts->cpu,
494 0, cpu_get_pc (interrupts->cpu),
499 cpu_push_all (interrupts->cpu);
500 addr = memory_read16 (interrupts->cpu,
501 interrupts->vectors_addr + id * 2);
502 cpu_call (interrupts->cpu, addr);
504 /* Now, protect from nested interrupts. */
507 cpu_set_ccr_X (interrupts->cpu, 1);
511 cpu_set_ccr_I (interrupts->cpu, 1);
515 h = &interrupts->interrupts_history[interrupts->history_index];
517 h->taken_cycle = cpu_current_cycle (interrupts->cpu);
518 h->raised_cycle = interrupts->interrupts[id].cpu_cycle;
520 if (interrupts->history_index >= MAX_INT_HISTORY-1)
521 interrupts->history_index = 0;
523 interrupts->history_index++;
525 interrupts->nb_interrupts_raised++;
526 cpu_add_cycles (interrupts->cpu, 14);
533 interrupts_raise (struct interrupts *interrupts, enum M6811_INT number)
535 interrupts->pending_mask |= (1 << number);
536 interrupts->nb_interrupts_raised ++;
540 interrupts_info (SIM_DESC sd, struct interrupts *interrupts)
545 sim_io_printf (sd, "Interrupts Info:\n");
546 sim_io_printf (sd, " Interrupts raised: %lu\n",
547 interrupts->nb_interrupts_raised);
549 if (interrupts->start_mask_cycle >= 0)
551 t = cpu_current_cycle (interrupts->cpu);
553 t -= interrupts->start_mask_cycle;
554 if (t > interrupts->max_mask_cycles)
555 interrupts->max_mask_cycles = t;
557 sim_io_printf (sd, " Current interrupts masked sequence: %s\n",
558 interrupts->cpu, t,
561 t = interrupts->min_mask_cycles == CYCLES_MAX ?
562 interrupts->max_mask_cycles :
563 interrupts->min_mask_cycles;
564 sim_io_printf (sd, " Shortest interrupts masked sequence: %s\n",
565 cycle_to_string (interrupts->cpu, t,
568 t = interrupts->max_mask_cycles;
569 sim_io_printf (sd, " Longest interrupts masked sequence: %s\n",
570 cycle_to_string (interrupts->cpu, t,
573 t = interrupts->last_mask_cycles;
574 sim_io_printf (sd, " Last interrupts masked sequence: %s\n",
575 cycle_to_string (interrupts->cpu, t,
578 if (interrupts->xirq_start_mask_cycle >= 0)
580 t = cpu_current_cycle (interrupts->cpu);
582 t -= interrupts->xirq_start_mask_cycle;
583 if (t > interrupts->xirq_max_mask_cycles)
584 interrupts->xirq_max_mask_cycles = t;
586 sim_io_printf (sd, " XIRQ Current interrupts masked sequence: %s\n",
587 cycle_to_string (interrupts->cpu, t,
591 t = interrupts->xirq_min_mask_cycles == CYCLES_MAX ?
592 interrupts->xirq_max_mask_cycles :
593 interrupts->xirq_min_mask_cycles;
594 sim_io_printf (sd, " XIRQ Min interrupts masked sequence: %s\n",
595 cycle_to_string (interrupts->cpu, t,
598 t = interrupts->xirq_max_mask_cycles;
599 sim_io_printf (sd, " XIRQ Max interrupts masked sequence: %s\n",
600 cycle_to_string (interrupts->cpu, t,
603 t = interrupts->xirq_last_mask_cycles;
604 sim_io_printf (sd, " XIRQ Last interrupts masked sequence: %s\n",
605 cycle_to_string (interrupts->cpu, t,
608 if (interrupts->pending_mask)
610 sim_io_printf (sd, " Pending interrupts : ");
613 enum M6811_INT int_number = interrupts->interrupt_order[i];
615 if (interrupts->pending_mask & (1 << int_number))
625 " Delta between interrupts\n");
632 which = interrupts->history_index - i - 1;
635 h = &interrupts->interrupts_history[which];
642 cycle_to_string (interrupts->cpu, h->taken_cycle, 0));
644 cycle_to_string (interrupts->cpu, dt, 0));
649 cycle_to_string (interrupts->cpu, dt, PRINT_TIME));
Indexes created Fri Apr 17 00:22:50 UTC 2026