Cross Reference: /src/external/gpl3/gdb/dist/sim/mips/dv-tx3904cpu.c

Lines Matching defs:controller
121   struct tx3904cpu *controller;
123   controller = HW_ZALLOC (me, struct tx3904cpu);
124   set_hw_data (me, controller);
129   controller->pending_level = 0;
130   controller->pending_reset = 0;
131   controller->pending_nmi = 0;
132   controller->event = NULL;
143   struct tx3904cpu *controller = hw_data (me);
151   if (controller->pending_reset)
153       controller->pending_reset = 0;
157   else if (controller->pending_nmi)
159       controller->pending_nmi = 0;
163   else if (controller->pending_level)
166 		 controller->pending_level,
173       if (controller->pending_level > 0) /* interrupt set */
176 	  CAUSE |= (controller->pending_level & cause_IP_mask) << cause_IP_shift;
180 	     (controller->pending_level & ((SR >> status_IM_shift) & status_IM_mask)))
182 	      controller->pending_level = 0;
188 	      if (controller->event != NULL)
189 		hw_event_queue_deschedule(me, controller->event);
190 	      controller->event =
207   struct tx3904cpu *controller = hw_data (me);
212       controller->pending_reset = 1;
217       controller->pending_nmi = 1;
224 	controller->pending_level = -1; /* signal end of interrupt */
226 	controller->pending_level = level;
237   if (controller->event != NULL)
238     hw_event_queue_deschedule(me, controller->event);
239   controller->event =
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