Cross Reference: /src/external/gpl3/gdb/dist/sim/mips/sim-main.c

Lines Matching defs:paddr
40    starting at physical location pAddr. The data is returned in the
59 	     address_word pAddr,
67   sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
75   if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
81 		    pr_addr (pAddr));
84   dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
94 	unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr);
100       value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
103       value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
106       value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
109       value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr);
112       value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr);
115       value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr);
118       value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr);
121       value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr);
129 	 (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
136 	/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
138 	value <<= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
140 	/* For little endian target, byte (pAddr&LOADDRMASK == 0)
142 	value <<= ((pAddr & LOADDRMASK) * 8);
158    physical location pAddr using the memory hierarchy (data caches and
163    memory need to be valid. The low-order two (or three) bits of pAddr
176 	      address_word pAddr,
180   sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
188   if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
192 		  pr_addr(pAddr));
194   dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
197   printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
204 	/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
206 	MemElem >>= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
208 	/* For little endian target, byte (pAddr&LOADDRMASK == 0)
210 	MemElem >>= ((pAddr & LOADDRMASK) * 8);
222 	sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val);
226       sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem);
229       sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem);
232       sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem);
235       sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem);
238       sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem);
241       sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem);
244       sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem);
247       sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem);
269   address_word paddr = vaddr;
274   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
275   LoadMemory (&memval, NULL, access, paddr, vaddr, isINSTRUCTION, isREAL);
293   address_word paddr = vaddr;
298   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
299   LoadMemory (&memval, NULL, access, paddr, vaddr, isINSTRUCTION, isREAL);
328 	  address_word pAddr,
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