Lines Matching defs:scpu
47 ((sim_core_read_aligned_1 (scpu, cia, read_map, addr) << 24) \
48 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+1) << 16) \
49 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+2) << 8) \
50 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+3)))
55 ((sim_core_read_aligned_1 (scpu, cia, read_map, addr) << 8) \
56 + (sim_core_read_aligned_1 (scpu, cia, read_map, addr+1))) << 16) >> 16)
149 wbat (sim_cpu *scpu, int32_t pc, int32_t x, int32_t v)
151 address_word cia = CPU_PC_GET (scpu);
153 sim_core_write_aligned_1 (scpu, cia, write_map, x, v);
159 wsat (sim_cpu *scpu, int32_t pc, int32_t x, int32_t v)
161 address_word cia = CPU_PC_GET (scpu);
163 sim_core_write_aligned_2 (scpu, cia, write_map, x, v);
169 wlat (sim_cpu *scpu, int32_t pc, int32_t x, int32_t v)
171 address_word cia = CPU_PC_GET (scpu);
173 sim_core_write_aligned_4 (scpu, cia, write_map, x, v);
179 rsat (sim_cpu *scpu, int32_t pc, int32_t x)
181 address_word cia = CPU_PC_GET (scpu);
183 return (sim_core_read_aligned_2 (scpu, cia, read_map, x));
189 rbat (sim_cpu *scpu, int32_t pc, int32_t x)
191 address_word cia = CPU_PC_GET (scpu);
193 return (sim_core_read_aligned_1 (scpu, cia, read_map, x));
199 rlat (sim_cpu *scpu, int32_t pc, int32_t x)
201 address_word cia = CPU_PC_GET (scpu);
203 return (sim_core_read_aligned_4 (scpu, cia, read_map, x));
231 TRACE_INSN (scpu, "0x%08x, %s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x", \
247 sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
248 address_word cia = CPU_PC_GET (scpu);
258 inst = (sim_core_read_aligned_1 (scpu, cia, read_map, pc) << 8)
259 + sim_core_read_aligned_1 (scpu, cia, read_map, pc+1);
343 sim_engine_halt (sd, scpu, NULL, pc, sim_stopped, SIM_SIGILL);
394 sim_engine_halt (sd, scpu, NULL, pc, sim_stopped, SIM_SIGILL);
408 sim_engine_halt (sd, scpu, NULL, pc, sim_stopped, SIM_SIGILL);
440 wlat (scpu, opc, sp, pc + 6);
444 wlat (scpu, opc, sp, cpu.asregs.regs[0]);
459 cpu.asregs.regs[0] = rlat (scpu, opc, sp);
463 pc = rlat (scpu, opc, sp) - 2;
491 wlat (scpu, opc, sp, cpu.asregs.regs[b]);
502 cpu.asregs.regs[b] = rlat (scpu, opc, sp);
512 cpu.asregs.regs[reg] = rlat (scpu, opc, addr);
522 wlat (scpu, opc, addr, cpu.asregs.regs[reg]);
534 cpu.asregs.regs[dest] = rlat (scpu, opc, xv);
543 wlat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
554 cpu.asregs.regs[a] = rlat (scpu, opc, addr);
566 wlat (scpu, opc, addr, cpu.asregs.regs[b]);
666 scpu, NULL, pc, sim_stopped, SIM_SIGILL);
681 wlat (scpu, opc, sp, pc + 2);
685 wlat (scpu, opc, sp, cpu.asregs.regs[0]);
719 cpu.asregs.regs[dest] = rbat (scpu, opc, xv);
728 cpu.asregs.regs[reg] = rbat (scpu, opc, addr);
738 wbat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
747 wbat (scpu, opc, addr, cpu.asregs.regs[reg]);
770 cpu.asregs.regs[dest] = rsat (scpu, opc, xv);
779 cpu.asregs.regs[reg] = rsat (scpu, opc, addr);
789 wsat (scpu, opc, cpu.asregs.regs[dest], cpu.asregs.regs[val]);
798 wsat (scpu, opc, addr, cpu.asregs.regs[reg]);
933 sim_engine_halt (sd, scpu, NULL, pc, sim_exited,
942 sim_core_read_buffer (sd, scpu, read_map, fname,
955 sim_core_write_buffer (sd, scpu, write_map, buf,
966 sim_core_read_buffer (sd, scpu, read_map, str,
977 sim_core_read_buffer (sd, scpu, read_map, fname,
994 wlat (scpu, opc, sp, pc + 6);
998 wlat (scpu, opc, sp, cpu.asregs.regs[0]);
1057 sim_engine_halt (sd, scpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
1068 cpu.asregs.regs[a] = rbat (scpu, opc, addr);
1080 wbat (scpu, opc, addr, cpu.asregs.regs[b]);
1092 cpu.asregs.regs[a] = rsat (scpu, opc, addr);
1104 wsat (scpu, opc, addr, cpu.asregs.regs[b]);
1111 sim_engine_halt (sd, scpu, NULL, pc, sim_stopped, SIM_SIGILL);
1127 moxie_reg_store (SIM_CPU *scpu, int rn, const void *memory, int length)
1147 moxie_reg_fetch (SIM_CPU *scpu, int rn, void *memory, int length)
1268 sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
1283 sim_core_write_buffer (sd, scpu, write_map, buf, 0xE0000000, size);
1294 sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
1313 wlat (scpu, 0, 0, 0);
1314 wlat (scpu, 0, 4, argc);
1322 wlat (scpu, 0, 4 + 4 + i * 4, tp);
1325 sim_core_write_buffer (sd, scpu, write_map, argv[i],
1330 wlat (scpu, 0, 4 + 4 + i * 4, 0);
Indexes created Thu May 14 00:25:00 UTC 2026