Cross Reference: /src/external/gpl3/gdb/dist/sim/ppc/powerpc.igen

Lines Matching refs:FRS
58 :scratch::::FRS:FRS:
59 :cache:::uint64_t *:frS:FRS:(cpu_registers(processor)->fpr + FRS)
60 :cache:::uint32_t:FRS_BITMASK:FRS:(1 << FRS)
1047 uint32_t::function::SINGLE:uint64_t FRS
1049 	if (EXTRACTED64(FRS, 1, 11) > 896
1050 	    || EXTRACTED64(FRS, 1, 63) == 0) {
1052 	  WORD = (INSERTED32(EXTRACTED64(FRS, 0, 1), 0, 1)
1053 	          | INSERTED32(EXTRACTED64(FRS, 5, 34), 2, 31));
1055 	else if (874 <= EXTRACTED64(FRS, 1, 11)
1056 	         && EXTRACTED64(FRS, 1, 11) <= 896) {
1058 	  int sign = EXTRACTED64(FRS, 0, 0);
1059 	  int exp = EXTRACTED64(FRS, 1, 11) - 1023;
1061 	                     | INSERTED64(EXTRACTED64(FRS, 12, 63), 1, 52));
1293 int::function::sign:uint64_t FRS
1294 	return (MASKED64(FRS, 0, 0)
1297 int::function::biased_exp:uint64_t frs, int single
1299 	  return EXTRACTED64(frs, 1, 8);
1301 	  return EXTRACTED64(frs, 1, 11);
1302 uint64_t::function::fraction:uint64_t frs, int single
1304 	  return EXTRACTED64(frs, 9, 31);
1306 	  return EXTRACTED64(frs, 12, 63);
1310 int::function::is_nor:uint64_t frs, int single
1311 	int exp = biased_exp(frs, single);
1314 int::function::is_zero:uint64_t FRS
1315 	return (MASKED64(FRS, 1, 63) == 0
1316 	        ? sign(FRS)
1318 int::function::is_den:uint64_t frs, int single
1319 	int exp = biased_exp(frs, single);
1320 	uint64_t frac = fraction(frs, single);
1322 	        ? sign(frs)
1324 int::function::is_inf:uint64_t frs, int single
1325 	int exp = biased_exp(frs, single);
1326 	uint64_t frac = fraction(frs, single);
1328 	        ? sign(frs)
1330 int::function::is_NaN:uint64_t frs, int single
1331 	int exp = biased_exp(frs, single);
1332 	uint64_t frac = fraction(frs, single);
1334 	        ? sign(frs)
1336 int::function::is_SNaN:uint64_t frs, int single
1337 	return (is_NaN(frs, single)
1338 	        && !(frs & (single ? MASK64(9, 9) : MASK64(12, 12)))
1339 	             ? sign(frs)
1341 int::function::is_QNaN:uint64_t frs, int single
1342 	return (is_NaN(frs, single) && !is_SNaN(frs, single));
3579 0.52,6.FRS,11.RA,16.D:D:f::Store Floating-Point Single
3589 	STORE(EA, 4, SINGLE(*frS));
3592 0.31,6.FRS,11.RA,16.RB,21.663,31./:X:f::Store Floating-Point Single Indexed
3602 	STORE(EA, 4, SINGLE(*frS));
3605 0.53,6.FRS,11.RA,16.D:D:f::Store Floating-Point Single with Update
3615 	STORE(EA, 4, SINGLE(*frS));
3619 0.31,6.FRS,11.RA,16.RB,21.695,31./:X:f::Store Floating-Point Single with Update Indexed
3629 	STORE(EA, 4, SINGLE(*frS));
3633 0.54,6.FRS,11.RA,16.D:D:f::Store Floating-Point Double
3643 	STORE(EA, 8, *frS);
3646 0.31,6.FRS,11.RA,16.RB,21.727,31./:X:f::Store Floating-Point Double Indexed
3656 	STORE(EA, 8, *frS);
3659 0.31,6.FRS,11.RA,16.RB,21.983,31./:X:f::Store Floating-Point Integer Word Indexed
3668 	STORE(EA, 4, *frS);
3671 0.55,6.FRS,11.RA,16.D:D:f::Store Floating-Point Double with Update
3681 	STORE(EA, 8, *frS);
3685 0.31,6.FRS,11.RA,16.RB,21.759,31./:X:f::Store Floating-Point Double with Update Indexed
3695 	STORE(EA, 8, *frS);
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