Lines Matching refs:SPR
81 #:compute:::int:SPR_is_256:SPR:(SPR == 256)
136 #define PPC_INSN_FROM_SPR(INT_MASK, SPR) \
139 ppc_insn_from_spr(MY_INDEX, cpu_model(processor), INT_MASK, SPR); \
142 #define PPC_INSN_TO_SPR(INT_MASK, SPR) \
145 ppc_insn_to_spr(MY_INDEX, cpu_model(processor), INT_MASK, SPR); \
187 #define PPC_NO_SPR (-1) /* flag for no SPR register */
200 int16_t spr_busy; /* SPR register that is busy or PPC_NO_SPR */
232 uint8_t spr_busy[nr_of_sprs]; /* SPR registers that are busy */
3346 0.31,6.RS,11.SPR,21.467,31./:XFX::mtspr %SPR, %RS:Move to Special Purpose Register
3351 int n = (SPR{5:9} << 5) | SPR{0:4};
3352 if (SPR{0} && IS_PROBLEM_STATE(processor))
3390 0.31,6.RT,11.SPR,21.339,31./:XFX::mfspr %RT, %SPR:Move from Special Purpose Register
3395 int n = (SPR{5:9} << 5) | SPR{0:4};
3396 if (SPR{0} && IS_PROBLEM_STATE(processor))
3419 /* NOTE - these SPR's are not readable. Use mftb[ul] */
4885 #0.31,6.RS,11.SPR,21.467,31./:XFX:::Move To Special Purpose Register
4886 #0.31,6.RT,11.SPR,21.339,31./:XFX:::Move From Special Purpose Register
Indexes created Wed Apr 29 00:23:26 UTC 2026