Cross Reference: /src/external/gpl3/gdb/dist/sim/riscv/sim-main.c

Lines Matching defs:shamt_imm
171   unsigned_word shamt_imm = ((iw >> OP_SH_SHAMT) & OP_MASK_SHAMT);
274 		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
275       if (RISCV_XLEN (cpu) == 32 && shamt_imm > 0x1f)
278       store_rd (cpu, rd, riscv_cpu->regs[rs1] << shamt_imm);
282 		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
285 		EXTEND32 ((uint32_t) riscv_cpu->regs[rs1] << shamt_imm));
303 		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
304       if (RISCV_XLEN (cpu) == 32 && shamt_imm > 0x1f)
307       store_rd (cpu, rd, riscv_cpu->regs[rs1] >> shamt_imm);
311 		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
314 		EXTEND32 ((uint32_t) riscv_cpu->regs[rs1] >> shamt_imm));
335 		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
338 	  if (shamt_imm > 0x1f)
341 	  tmp = ashiftrt (riscv_cpu->regs[rs1], shamt_imm);
344 	tmp = ashiftrt64 (riscv_cpu->regs[rs1], shamt_imm);
349 		  rd_name, rs1_name, shamt_imm, rd_name, rs1_name, shamt_imm);
352 	ashiftrt ((int32_t) riscv_cpu->regs[rs1], shamt_imm)));
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