Lines Matching refs:req
583 ata_command(struct atareq *req)
589 error = ioctl(fd, ATAIOCCOMMAND, req);
597 error = satl_command(req, 16);
603 (void) satl_command(req, 12);
607 switch (req->retsts) {
618 if (req->error & WDCE_ABRT)
623 "%0x\n", req->error);
627 "%d\n", req->retsts);
636 satl_command(struct atareq *req, int cmdlen)
648 if (req->datalen > 0) {
649 if (req->flags & ATACMD_READ)
656 if (req->datalen > 0) {
661 if (req->datalen == 0 || req->flags & ATACMD_READ)
670 c.cmd16.features[1] = req->features;
672 c.cmd16.sector_count[1] = req->sec_count;
674 c.cmd16.lba[1] = req->sec_num;
676 c.cmd16.lba[3] = req->cylinder;
678 c.cmd16.lba[5] = req->cylinder >> 8;
680 c.cmd16.ata_cmd = req->command;
687 c.cmd12.features[0] = req->features;
688 c.cmd12.sector_count[0] = req->sec_count;
689 c.cmd12.lba[0] = req->sec_num;
690 c.cmd12.lba[1] = req->cylinder;
691 c.cmd12.lba[2] = req->cylinder >> 8;
694 c.cmd12.ata_cmd = req->command;
705 sreq.databuf = req->databuf;
706 sreq.datalen = req->datalen;
708 sreq.timeout = req->timeout;
711 if (req->flags & ATACMD_READ)
713 if (req->flags & ATACMD_WRITE)
721 req->datalen = sreq.datalen_used;
722 req->retsts = ATACMD_OK;
723 req->error = 0;
755 req->sec_count = desc[5];
756 req->sec_num = desc[7];
757 req->head = (desc[12] & 0xf0) |
759 req->cylinder = desc[11] << 8 | desc[9];
760 req->retsts = desc[13];
761 req->error = desc[3];
1163 struct atareq req;
1175 memset(&req, 0, sizeof(req));
1177 req.flags = ATACMD_READ;
1178 req.command = WDCC_IDENTIFY;
1179 req.databuf = &inbuf;
1180 req.datalen = sizeof(inbuf);
1181 req.timeout = 1000;
1183 ata_command(&req);
1512 struct atareq req;
1518 memset(&req, 0, sizeof(req));
1521 req.command = WDCC_IDLE_IMMED;
1523 req.command = WDCC_STANDBY_IMMED;
1525 req.command = WDCC_SLEEP;
1527 req.timeout = 1000;
1529 ata_command(&req);
1542 struct atareq req;
1545 memset(&req, 0, sizeof(req));
1547 req.command = SET_FEATURES;
1548 req.timeout = 1000;
1551 req.features = WDSF_APM_DS;
1555 req.features = WDSF_APM_EN;
1556 req.sec_count = l + 1;
1562 ata_command(&req);
1575 struct atareq req;
1600 memset(&req, 0, sizeof(req));
1603 req.sec_count = idle / 5;
1605 req.sec_count = idle / (30*60) + 240;
1607 req.command = cmdname[3] == 's' ? WDCC_STANDBY : WDCC_IDLE;
1608 req.timeout = 1000;
1610 ata_command(&req);
1622 struct atareq req;
1628 memset(&req, 0, sizeof(req));
1630 req.command = WDCC_CHECK_PWR;
1631 req.timeout = 1000;
1632 req.flags = ATACMD_READREG;
1634 ata_command(&req);
1638 switch (req.sec_count) {
1649 printf("Unknown power code (%02x)\n", req.sec_count);
1663 struct atareq req;
1671 memset(&req, 0, sizeof(req));
1673 req.features = WDSM_ENABLE_OPS;
1674 req.command = WDCC_SMART;
1675 req.cylinder = WDSMART_CYL;
1676 req.timeout = 1000;
1678 ata_command(&req);
1682 memset(&req, 0, sizeof(req));
1684 req.features = WDSM_DISABLE_OPS;
1685 req.command = WDCC_SMART;
1686 req.cylinder = WDSMART_CYL;
1687 req.timeout = 1000;
1689 ata_command(&req);
1705 memset(&req, 0, sizeof(req));
1707 req.features = WDSM_STATUS;
1708 req.command = WDCC_SMART;
1709 req.cylinder = WDSMART_CYL;
1710 req.timeout = 1000;
1712 ata_command(&req);
1714 if (req.cylinder != WDSMART_CYL) {
1724 memset(&req, 0, sizeof(req));
1726 req.flags = ATACMD_READ;
1727 req.features = WDSM_RD_DATA;
1728 req.command = WDCC_SMART;
1729 req.databuf = (caddr_t) inbuf;
1730 req.datalen = sizeof(inbuf);
1731 req.cylinder = WDSMART_CYL;
1732 req.timeout = 1000;
1734 ata_command(&req);
1737 memset(&req, 0, sizeof(req));
1739 req.flags = ATACMD_READ;
1740 req.features = WDSM_RD_THRESHOLDS;
1741 req.command = WDCC_SMART;
1742 req.databuf = (caddr_t) inbuf2;
1743 req.datalen = sizeof(inbuf2);
1744 req.cylinder = WDSMART_CYL;
1745 req.timeout = 1000;
1747 ata_command(&req);
1764 memset(&req, 0, sizeof(req));
1766 req.features = WDSM_EXEC_OFFL_IMM;
1767 req.command = WDCC_SMART;
1768 req.cylinder = WDSMART_CYL;
1769 req.sec_num = atol(argv[1]);
1770 req.timeout = 10000;
1772 ata_command(&req);
1780 memset(&req, 0, sizeof(req));
1782 req.flags = ATACMD_READ;
1783 req.features = WDSM_RD_LOG;
1784 req.sec_count = 1;
1785 req.sec_num = 1;
1786 req.command = WDCC_SMART;
1787 req.databuf = (caddr_t) inbuf;
1788 req.datalen = sizeof(inbuf);
1789 req.cylinder = WDSMART_CYL;
1790 req.timeout = 1000;
1792 ata_command(&req);
1802 memset(&req, 0, sizeof(req));
1804 req.flags = ATACMD_READ;
1805 req.features = WDSM_RD_LOG;
1806 req.sec_count = 1;
1807 req.sec_num = 6;
1808 req.command = WDCC_SMART;
1809 req.databuf = (caddr_t) inbuf;
1810 req.datalen = sizeof(inbuf);
1811 req.cylinder = WDSMART_CYL;
1812 req.timeout = 1000;
1814 ata_command(&req);
1827 struct atareq req;
1835 memset(&req, 0, sizeof(req));
1840 req.command = WDCC_SECURITY_FREEZE;
1841 req.timeout = 1000;
1842 ata_command(&req);
1865 req.flags |= ATACMD_WRITE;
1866 req.timeout = 1000;
1867 req.databuf = data;
1868 req.datalen = sizeof(data);
1880 req.command = WDCC_SECURITY_SET_PASSWORD;
1882 req.command = WDCC_SECURITY_UNLOCK;
1884 req.command = WDCC_SECURITY_DISABLE_PASSWORD;
1902 req
1911 req.timeout = (inqbuf->atap_eseu_time & 0xff)
1914 req.timeout = (inqbuf->atap_seu_time & 0xff)
1924 if (req.timeout == 30600000) {
1929 req.timeout = INT_MAX;
1931 req.timeout = timeout;
1935 (req.timeout / 1000 / 60) / 60,
1936 (req.timeout / 1000 / 60) % 60,
1937 req.timeout % 60);
1942 ata_command(&req);
Indexes created Thu Oct 30 16:09:53 GMT 2025