Lines Matching refs:x101
82 #define TS_C_CSC 0x101##a000##0000UL /* Cchip System Configuration */
88 #define TS_C_MTR 0x101##a000##0040UL
90 #define TS_C_MISC 0x101##a000##0080UL /* Miscellaneous Register */
96 #define TS_C_MPD 0x101##a000##00c0UL
103 #define TS_C_AAR0 0x101##a000##0100UL
104 #define TS_C_AAR1 0x101##a000##0140UL
105 #define TS_C_AAR2 0x101##a000##0180UL
106 #define TS_C_AAR3 0x101##a000##01c0UL
111 #define TS_C_DIM0 0x101##a000##0200UL
112 #define TS_C_DIM1 0x101##a000##0240UL
113 #define TS_C_DIR0 0x101##a000##0280UL
114 #define TS_C_DIR1 0x101##a000##02c0UL
115 #define TS_C_DRIR 0x101##a000##0300UL
116 #define TS_C_PRBEN 0x101##a000##0340UL
117 #define TS_C_IIC0 0x101##a000##0380UL
118 #define TS_C_IIC1 0x101##a000##03c0UL
119 #define TS_C_MPR0 0x101##a000##0400UL
120 #define TS_C_MPR1 0x101##a000##0440UL
121 #define TS_C_MPR2 0x101##a000##0480UL
122 #define TS_C_MPR3 0x101##a000##04c0UL
123 #define TS_C_MCTL 0x101##a000##0500UL
125 #define TS_C_TTR 0x101##a000##0580UL
126 #define TS_C_TDR 0x101##a000##05c0UL
127 #define TS_C_DIM2 0x101##a000##0600UL
128 #define TS_C_DIM3 0x101##a000##0640UL
129 #define TS_C_DIR2 0x101##a000##0680UL
130 #define TS_C_DIR3 0x101##a000##06c0UL
131 #define TS_C_IIC2 0x101##a000##0700UL
132 #define TS_C_IIC3 0x101##a000##0740UL
138 #define TS_D_DSC 0x101##b000##0800UL
139 #define TS_D_STR 0x101##b000##0840UL
140 #define TS_D_DREV 0x101##b000##0880UL
141 #define TS_D_DSC2 0x101##b000##08c0UL
Indexes created Thu Oct 23 18:09:57 GMT 2025