Lines Matching defs:fsc
145 struct flsc_softc *fsc = device_private(self);
146 struct ncr53c9x_softc *sc = &fsc->sc_ncr53c9x;
159 fsc->sc_dmabase = (volatile uint8_t *)zap->va;
160 fsc->sc_reg = &((volatile uint8_t *)zap->va)[0x1000001];
164 aprint_normal(": address %p", fsc->sc_reg);
195 fsc->sc_portbits = 0xa0 | FLSC_PB_EDI | FLSC_PB_ESI;
196 fsc->sc_hardbits = fsc->sc_reg[0x40];
198 fsc->sc_alignbuf = (uint8_t *)((u_long)fsc->sc_unalignbuf & -4);
209 fsc->sc_isr.isr_intr = ncr53c9x_intr;
210 fsc->sc_isr.isr_arg = sc;
211 fsc->sc_isr.isr_ipl = 2;
212 add_isr(&fsc->sc_isr);
214 fsc->sc_reg[0x40] = fsc->sc_portbits;
231 struct flsc_softc *fsc = (struct flsc_softc *)sc;
233 return fsc->sc_reg[reg * 4];
239 struct flsc_softc *fsc = (struct flsc_softc *)sc;
243 if (fsc->sc_piomode && reg == NCR_CMD &&
282 fsc->sc_reg[reg * 4] = v;
288 struct flsc_softc *fsc = (struct flsc_softc *)sc;
291 hardbits = fsc->sc_reg[0x40];
293 return (fsc->sc_csr = 0);
296 fsc->sc_portbits |= FLSC_PB_LED;
298 fsc->sc_portbits &= ~FLSC_PB_LED;
301 (fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) != 0) {
305 if (fsc->sc_piomode && (fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) != 0 &&
309 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS;
310 fsc->sc_reg[0x40] = fsc->sc_portbits;
317 struct flsc_softc *fsc = (struct flsc_softc *)sc;
319 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS;
320 fsc->sc_reg[0x40] = fsc->sc_portbits;
326 struct flsc_softc *fsc = (struct flsc_softc *)sc;
333 if (fsc->sc_active) {
335 *fsc->sc_dmaaddr, fsc->sc_dmasize,
336 fsc->sc_reg[NCR_STAT * 4], ti->flags, ti->offset);
338 ti->period, fsc->sc_reg[NCR_FFLAG * 4],
339 fsc->sc_reg[NCR_INTR * 4]);
344 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS;
345 fsc->sc_reg[0x40] = fsc->sc_portbits;
346 fsc->sc_reg[0x80] = 0;
347 *((volatile uint32_t *)fsc->sc_dmabase) = 0;
348 fsc->sc_active = 0;
349 fsc->sc_piomode = 0;
355 register struct flsc_softc *fsc = (struct flsc_softc *)sc;
362 fsc->sc_piomode, fsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
363 fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
364 if ((fsc->sc_reg[0x40] & FLSC_HB_CREQ) == 0)
365 printf("flsc_dma_intr: csr %x stat %x intr %x\n", fsc->sc_csr,
367 if (fsc->sc_active == 0) {
373 if (fsc->sc_piomode == 0) {
374 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS;
375 fsc->sc_reg[0x40] = fsc->sc_portbits;
376 fsc->sc_reg[0x80] = 0;
377 *((volatile uint32_t *)fsc->sc_dmabase) = 0;
378 cnt = fsc->sc_reg[NCR_TCL * 4];
379 cnt += fsc->sc_reg[NCR_TCM * 4] << 8;
380 cnt += fsc->sc_reg[NCR_TCH * 4] << 16;
381 if (!fsc->sc_datain) {
382 cnt += fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
383 fsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
385 cnt = fsc->sc_dmasize - cnt; /* number of bytes transferred */
387 if (fsc->sc_xfr_align) {
390 (*fsc->sc_dmaaddr)[i] = fsc->sc_alignbuf[i];
391 fsc->sc_xfr_align = 0;
393 *fsc->sc_dmaaddr += cnt;
394 *fsc->sc_pdmalen -= cnt;
395 fsc->sc_active = 0;
400 fsc->sc_active = 0;
401 fsc->sc_piomode = 0;
406 cnt = fsc->sc_dmasize;
413 p = *fsc->sc_dmaaddr;
417 cmdreg = fsc->sc_reg + NCR_CMD * 4;
418 fiforeg = fsc->sc_reg + NCR_FIFO * 4;
419 statreg = fsc->sc_reg + NCR_STAT * 4;
420 intrreg = fsc->sc_reg + NCR_INTR * 4;
422 cnt, fsc->sc_datain, flscphase, flscstat, flscintr));
424 if (fsc->sc_datain) {
430 fsc->sc_active = 0;
434 fsc->sc_active));
438 n = 16 - (fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF);
446 fsc->sc_active = 0;
450 if (fsc->sc_active && cnt) {
459 } while (cnt && fsc->sc_active && (flscintr & NCRINTR_BS) != 0);
461 if (fsc->sc_dmasize < 8 && cnt)
463 fsc->sc_dmasize, cnt);
466 *fsc->sc_pdmalen, fsc->sc_dmasize, cnt, flscphase, flscstat, flscintr));
470 *fsc->sc_dmaaddr = p;
471 *fsc->sc_pdmalen -= fsc->sc_dmasize - cnt;
472 fsc->sc_dmasize = cnt;
474 if (*fsc->sc_pdmalen == 0) {
476 fsc->sc_piomode = 0;
485 struct flsc_softc *fsc = (struct flsc_softc *)sc;
490 fsc->sc_dmaaddr = addr;
491 fsc->sc_pdmalen = len;
492 fsc->sc_datain = datain;
493 fsc->sc_dmasize = *dmasize;
496 *dmasize = fsc->sc_dmasize;
498 fsc->sc_dmasize, *len));
499 fsc->sc_piomode = 1;
502 n = fsc->sc_dmasize;
506 fsc->sc_reg[NCR_FIFO * 4] = **fsc->sc_dmaaddr;
507 (*fsc->sc_pdmalen)--;
508 (*fsc->sc_dmaaddr)++;
509 --fsc->sc_dmasize;
522 fsc->sc_dmasize > flsc_max_dma)
523 fsc->sc_dmasize = flsc_max_dma;
526 xfer = uimin(fsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1)));
527 fsc->sc_xfr_align = 0;
528 fsc->sc_piomode = 0;
529 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS;
530 fsc->sc_reg[0x40] = fsc->sc_portbits;
531 fsc->sc_reg[0x80] = 0;
532 *((volatile uint32_t *)fsc->sc_dmabase) = 0;
537 if (datain == 0 && fsc->sc_dmasize < 16) {
539 for (n = 0; n < fsc->sc_dmasize; ++n)
540 fsc->sc_reg[NCR_FIFO * 4] = *ptr++;
542 fsc->sc_piomode = 1;
543 fsc->sc_active = 1;
544 *fsc->sc_pdmalen -= fsc->sc_dmasize;
545 *fsc->sc_dmaaddr += fsc->sc_dmasize;
546 *dmasize = fsc->sc_dmasize;
547 fsc->sc_dmasize = 0;
559 fsc->sc_reg[NCR_FIFO * 4] = *ptr++;
565 pa = kvtop((void *)fsc->sc_alignbuf);
566 xfer = fsc->sc_dmasize = uimin(xfer, sizeof(fsc->sc_unalignbuf));
568 fsc->sc_xfr_align = 1;
574 else if (fsc->sc_dmasize < 4) {
576 fsc->sc_dmasize));
577 pa = kvtop((void *)fsc->sc_alignbuf);
578 fsc->sc_xfr_align = 1;
584 fsc->sc_dmasize &= -4;
588 while (xfer < fsc->sc_dmasize) {
591 if ((fsc->sc_dmasize - xfer) < PAGE_SIZE)
592 xfer = fsc->sc_dmasize;
597 fsc->sc_dmasize = xfer;
598 *dmasize = fsc->sc_dmasize;
599 fsc->sc_pa = pa;
602 if (fsc->sc_xfr_align) {
604 for (n = 0; n < sizeof(fsc->sc_unalignbuf); ++n)
605 fsc->sc_alignbuf[n] = n | 0x80;
606 dma_cachectl(fsc->sc_alignbuf,
607 sizeof(fsc->sc_unalignbuf));
610 dma_cachectl(*fsc->sc_dmaaddr, fsc->sc_dmasize);
613 fsc->sc_reg[0x80] = 0;
614 *((volatile uint32_t *)(fsc->sc_dmabase + (pa & 0x00fffffc))) = pa;
615 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS;
616 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA |
617 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE);
618 fsc->sc_reg[0x40] = fsc->sc_portbits;
620 ptr, pa, fsc->sc_dmasize, *len));
621 fsc->sc_active = 1;
628 struct flsc_softc *fsc = (struct flsc_softc *)sc;
630 NCR_DMA(("flsc_dma_go: datain %d size %d\n", fsc->sc_datain,
631 fsc->sc_dmasize));
633 fsc->sc_active = 1;
635 } else if (fsc->sc_piomode == 0) {
636 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS;
637 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA |
638 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE);
639 fsc->sc_reg[0x40] = fsc->sc_portbits;
646 struct flsc_softc *fsc = (struct flsc_softc *)sc;
648 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS;
649 fsc->sc_reg[0x40] = fsc->sc_portbits;
651 fsc->sc_reg[0x80] = 0;
652 *((volatile uint32_t *)fsc->sc_dmabase) = 0;
653 fsc->sc_piomode = 0;
659 struct flsc_softc *fsc = (struct flsc_softc *)sc;
661 return fsc->sc_active;
Indexes created Tue Sep 30 11:09:46 GMT 2025