Lines Matching refs:sc_reg
160 fsc->sc_reg = &((volatile uint8_t *)zap->va)[0x1000001];
164 aprint_normal(": address %p", fsc->sc_reg);
196 fsc->sc_hardbits = fsc->sc_reg[0x40];
214 fsc->sc_reg[0x40] = fsc->sc_portbits;
233 return fsc->sc_reg[reg * 4];
282 fsc->sc_reg[reg * 4] = v;
291 hardbits = fsc->sc_reg[0x40];
301 (fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) != 0) {
305 if (fsc->sc_piomode && (fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) != 0 &&
309 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS;
310 fsc->sc_reg[0x40] = fsc->sc_portbits;
319 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS;
320 fsc->sc_reg[0x40] = fsc->sc_portbits;
336 fsc->sc_reg[NCR_STAT * 4], ti->flags, ti->offset);
338 ti->period, fsc->sc_reg[NCR_FFLAG * 4],
339 fsc->sc_reg[NCR_INTR * 4]);
345 fsc->sc_reg[0x40] = fsc->sc_portbits;
346 fsc->sc_reg[0x80] = 0;
363 fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
364 if ((fsc->sc_reg[0x40] & FLSC_HB_CREQ) == 0)
375 fsc->sc_reg[0x40] = fsc->sc_portbits;
376 fsc->sc_reg[0x80] = 0;
378 cnt = fsc->sc_reg[NCR_TCL * 4];
379 cnt += fsc->sc_reg[NCR_TCM * 4] << 8;
380 cnt += fsc->sc_reg[NCR_TCH * 4] << 16;
382 cnt += fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
383 fsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
417 cmdreg = fsc->sc_reg + NCR_CMD * 4;
418 fiforeg = fsc->sc_reg + NCR_FIFO * 4;
419 statreg = fsc->sc_reg + NCR_STAT * 4;
420 intrreg = fsc->sc_reg + NCR_INTR * 4;
438 n = 16 - (fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF);
506 fsc->sc_reg[NCR_FIFO * 4] = **fsc->sc_dmaaddr;
530 fsc->sc_reg[0x40] = fsc->sc_portbits;
531 fsc->sc_reg[0x80] = 0;
540 fsc->sc_reg[NCR_FIFO * 4] = *ptr++;
559 fsc->sc_reg[NCR_FIFO * 4] = *ptr++;
613 fsc->sc_reg[0x80] = 0;
618 fsc->sc_reg[0x40] = fsc->sc_portbits;
639 fsc->sc_reg[0x40] = fsc->sc_portbits;
649 fsc->sc_reg[0x40] = fsc->sc_portbits;
651 fsc->sc_reg[0x80] = 0;