Lines Matching refs:ba
585 volatile void *ba;
592 ba = gp->g_regkva;
607 vgaw(ba, SREG_VIDEO_SUBS_ENABLE, 0x01);
609 vgaw(ba, GREG_MISC_OUTPUT_W, 0x03);
611 WCrt(ba, CRT_ID_REGISTER_LOCK_1, 0x48); /* unlock S3 VGA regs */
612 WCrt(ba, CRT_ID_REGISTER_LOCK_2, 0xA5); /* unlock syscontrol */
614 WCrt(ba, CRT_ID_EXT_MISC_CNTL_1, 0x02);
615 WCrt(ba, CRT_ID_EXT_MISC_CNTL_1, 0x00);
617 WSeq(ba, SEQ_ID_UNLOCK_EXT, 0x06); /* Unlock extensions */
626 vgaw(ba, GREG_MISC_OUTPUT_W, 0xC3);
629 WSeq(ba, SEQ_ID_RESET, 0x03);
631 WSeq(ba, SEQ_ID_CLOCKING_MODE, 0x01); /* 8 Dot Clock */
632 WSeq(ba, SEQ_ID_MAP_MASK, 0x0F); /* Enable write planes */
633 WSeq(ba, SEQ_ID_CHAR_MAP_SELECT, 0x00); /* Character Font */
635 WSeq(ba, SEQ_ID_MEMORY_MODE, 0x02); /* Complete mem access */
636 WSeq(ba, SEQ_ID_MMIO_SELECT, 0x00);
638 test = RSeq(ba, SEQ_ID_BUS_REQ_CNTL); /* Bus Request */
642 WSeq(ba, SEQ_ID_BUS_REQ_CNTL, test);
646 WSeq(ba, SEQ_ID_RAMDAC_CNTL, 0xC0);
648 WSeq(ba, SEQ_ID_UNKNOWN6, 0x00);
649 WSeq(ba, SEQ_ID_SIGNAL_SELECT, 0x02);
652 test = RSeq(ba, SEQ_ID_CLKSYN_CNTL_2); /* Clksyn2 read */
661 WSeq(ba, SEQ_ID_CLKSYN_CNTL_2, test);
666 WSeq(ba, SEQ_ID_MCLK_HI, test); /* PLL N-Divider Value */
669 WSeq(ba, SEQ_ID_MCLK_LO, test); /* PLL M-Divider Value */
673 WSeq(ba, SEQ_ID_DCLK_HI, 0x13);
674 WSeq(ba, SEQ_ID_DCLK_LO, 0x41);
676 test = RSeq (ba, SEQ_ID_CLKSYN_CNTL_2);
680 WSeq(ba,SEQ_ID_CLKSYN_CNTL_2, test);
683 test = vgar(ba, 0x3cc);
685 vgaw(ba, 0x3c2, test);
688 WSeq(ba, SEQ_ID_CLKSYN_CNTL_2, 0x02);
690 WCrt(ba, CRT_ID_HOR_TOTAL, 0x5F);
691 WCrt(ba, CRT_ID_HOR_DISP_ENA_END, 0x4F);
692 WCrt(ba, CRT_ID_START_HOR_BLANK, 0x50);
693 WCrt(ba, CRT_ID_END_HOR_BLANK, 0x82);
694 WCrt(ba, CRT_ID_START_HOR_RETR, 0x54);
695 WCrt(ba, CRT_ID_END_HOR_RETR, 0x80);
696 WCrt(ba, CRT_ID_VER_TOTAL, 0xBF);
698 WCrt(ba, CRT_ID_OVERFLOW, 0x1F); /* overflow reg */
700 WCrt(ba, CRT_ID_PRESET_ROW_SCAN, 0x00); /* no panning */
702 WCrt(ba, CRT_ID_MAX_SCAN_LINE, 0x40); /* vscan */
704 WCrt(ba, CRT_ID_CURSOR_START, 0x00);
705 WCrt(ba, CRT_ID_CURSOR_END, 0x00);
708 WCrt(ba, CRT_ID_START_ADDR_HIGH, 0x00);
709 WCrt(ba, CRT_ID_START_ADDR_LOW, 0x00);
712 WCrt(ba, CRT_ID_CURSOR_LOC_HIGH, 0x00);
713 WCrt(ba, CRT_ID_CURSOR_LOC_LOW, 0x00);
716 WCrt(ba, CRT_ID_START_VER_RETR, 0x9C);
717 WCrt(ba, CRT_ID_END_VER_RETR, 0x0E);
719 WCrt(ba, CRT_ID_VER_DISP_ENA_END, 0x8F);
720 WCrt(ba, CRT_ID_SCREEN_OFFSET, 0x50);
722 WCrt(ba, CRT_ID_UNDERLINE_LOC, 0x00);
724 WCrt(ba, CRT_ID_START_VER_BLANK, 0x96);
725 WCrt(ba, CRT_ID_END_VER_BLANK, 0xB9);
727 WCrt(ba, CRT_ID_MODE_CONTROL, 0xE3);
729 WCrt(ba, CRT_ID_LINE_COMPARE, 0xFF);
731 WCrt(ba, CRT_ID_SYSTEM_CONFIG, 0x21);
732 WCrt(ba, CRT_ID_MEMORY_CONF, 0x04);
733 WCrt(ba, CRT_ID_BACKWAD_COMP_1, 0x00);
734 WCrt(ba, CRT_ID_BACKWAD_COMP_2, 0x02);
735 WCrt(ba, CRT_ID_BACKWAD_COMP_3, 0x10); /* FIFO enabled */
738 WCrt(ba, CRT_ID_MISC_1, 0x35);
741 WCrt(ba, CRT_ID_DISPLAY_FIFO, 0x5A);
743 WCrt(ba, CRT_ID_EXT_MEM_CNTL_2, 0x02);
745 WCrt(ba, CRT_ID_LAW_POS_LO, 0x40);
747 WCrt(ba, CRT_ID_EXT_MISC_CNTL_1, 0x81);
748 WCrt(ba, CRT_ID_MISC_1, 0xB5);
749 WCrt(ba, CRT_ID_CONFIG_1, 0x0E);
751 WGfx(ba, GCT_ID_SET_RESET, 0x00);
752 WGfx(ba, GCT_ID_ENABLE_SET_RESET, 0x00);
753 WGfx(ba, GCT_ID_COLOR_COMPARE, 0x00);
754 WGfx(ba, GCT_ID_DATA_ROTATE, 0x00);
755 WGfx(ba, GCT_ID_READ_MAP_SELECT, 0x00);
756 WGfx(ba, GCT_ID_GRAPHICS_MODE, 0x40);
757 WGfx(ba, GCT_ID_MISC, 0x01);
758 WGfx(ba, GCT_ID_COLOR_XCARE, 0x0F);
759 WGfx(ba, GCT_ID_BITMASK, 0xFF);
763 WAttr (ba, i, i);
765 WAttr(ba, ACT_ID_ATTR_MODE_CNTL, 0x41);
766 WAttr(ba, ACT_ID_OVERSCAN_COLOR, 0x01);
767 WAttr(ba, ACT_ID_COLOR_PLANE_ENA, 0x0F);
768 WAttr(ba, ACT_ID_HOR_PEL_PANNING, 0x00);
769 WAttr(ba, ACT_ID_COLOR_SELECT, 0x00);
784 WCrt(ba, CRT_ID_HWGC_MODE, 0x00);
787 WCrt(ba, CRT_ID_LAW_CNTL, 0x13);
792 WCrt(ba, CRT_ID_LAW_CNTL, 0x13); /* 4 MB */
795 WCrt(ba, CRT_ID_LAW_CNTL, 0x12); /* 2 MB */
811 WAttr(ba, 0x33, 0);
815 gi->gd_regaddr = (void *) kvtop (__UNVOLATILE(ba));
875 volatile void *ba;
877 ba = gp->g_regkva;
878 cv3d_gfx_on_off(on > 0 ? 0 : 1, ba);
886 volatile void *ba;
889 ba = gp->g_regkva;
890 r = RSeq(ba, SEQ_ID_CLOCKING_MODE);
1211 volatile void *ba;
1232 ba = gp->g_regkva;
1235 cv3d_gfx_on_off(1, ba);
1285 cr66 = RCrt(ba, CRT_ID_EXT_MISC_CNTL_1);
1295 WCrt(ba, CRT_ID_EXT_MISC_CNTL_1, cr66);
1324 hvsync_pulse = vgar(ba, GREG_MISC_OUTPUT_R);
1333 vgaw(ba, GREG_MISC_OUTPUT_W, hvsync_pulse);
1336 WCrt(ba, CRT_ID_HWGC_MODE, 0x00);
1337 WCrt(ba, CRT_ID_EXT_DAC_CNTL, 0x00);
1339 WSeq(ba, SEQ_ID_MEMORY_MODE, (TEXT || (gv->depth == 1)) ? 0x06 : 0x0e);
1340 WGfx(ba, GCT_ID_READ_MAP_SELECT, 0x00);
1341 WSeq(ba, SEQ_ID_MAP_MASK, (gv->depth == 1) ? 0x01 : 0xff);
1342 WSeq(ba, SEQ_ID_CHAR_MAP_SELECT, 0x00);
1347 WSeq(ba, SEQ_ID_DCLK_HI, ((mnr & 0xFF00) >> 8));
1348 WSeq(ba, SEQ_ID_DCLK_LO, (mnr & 0xFF));
1352 WCrt(ba, CRT_ID_EXT_HOR_OVF,
1361 WCrt(ba, CRT_ID_EXT_VER_OVF,
1368 WCrt(ba, CRT_ID_HOR_TOTAL, HT);
1369 WCrt(ba, CRT_ID_DISPLAY_FIFO, HT - 5);
1371 WCrt(ba, CRT_ID_HOR_DISP_ENA_END, ((HDE >= HBS) ? (HBS - 1) : HDE));
1372 WCrt(ba, CRT_ID_START_HOR_BLANK, HBS);
1373 WCrt(ba, CRT_ID_END_HOR_BLANK, ((HBE & 0x1f) | 0x80));
1374 WCrt(ba, CRT_ID_START_HOR_RETR, HSS);
1375 WCrt(ba, CRT_ID_END_HOR_RETR,
1378 WCrt(ba, CRT_ID_VER_TOTAL, VT);
1379 WCrt(ba, CRT_ID_OVERFLOW,
1389 WCrt(ba, CRT_ID_MAX_SCAN_LINE,
1395 WCrt(ba, CRT_ID_MODE_CONTROL, 0xE3);
1401 WCrt(ba, CRT_ID_CURSOR_START, (md->fy & 0x1f) - 2);
1402 WCrt(ba, CRT_ID_CURSOR_END, (md->fy & 0x1f) - 1);
1404 WCrt(ba, CRT_ID_CURSOR_START, 0x00);
1405 WCrt(ba, CRT_ID_CURSOR_END, md->fy & 0x1f);
1407 WCrt(ba, CRT_ID_UNDERLINE_LOC, (md->fy - 1) & 0x1f);
1409 WCrt(ba, CRT_ID_CURSOR_LOC_HIGH, 0x00);
1410 WCrt(ba, CRT_ID_CURSOR_LOC_LOW, 0x00);
1413 WCrt(ba, CRT_ID_START_ADDR_HIGH, 0x00);
1414 WCrt(ba, CRT_ID_START_ADDR_LOW, 0x00);
1416 WCrt(ba, CRT_ID_START_VER_RETR, VSS);
1417 WCrt(ba, CRT_ID_END_VER_RETR, (VSE & 0x0f));
1418 WCrt(ba, CRT_ID_VER_DISP_ENA_END, VDE);
1419 WCrt(ba, CRT_ID_START_VER_BLANK, VBS);
1420 WCrt(ba, CRT_ID_END_VER_BLANK, VBE);
1422 WCrt(ba, CRT_ID_LINE_COMPARE, 0xff);
1423 WCrt(ba, CRT_ID_LACE_RETR_START, HT / 2);
1424 WCrt(ba, CRT_ID_LACE_CONTROL,
1427 WGfx(ba, GCT_ID_GRAPHICS_MODE,
1429 WGfx(ba, GCT_ID_MISC, (TEXT ? 0x04 : 0x01));
1431 WSeq (ba, SEQ_ID_MEMORY_MODE,
1437 test = RCrt(ba, CRT_ID_BACKWAD_COMP_2);
1438 WCrt(ba, CRT_ID_BACKWAD_COMP_2, (test | 0x20));
1440 sr15 = RSeq(ba, SEQ_ID_CLKSYN_CNTL_2);
1442 sr18 = RSeq(ba, SEQ_ID_RAMDAC_CNTL);
1447 test = RCrt(ba, CRT_ID_EXT_MISC_CNTL_2);
1498 WCrt(ba, CRT_ID_EXT_MISC_CNTL_2, clock_mode | test);
1499 WSeq(ba, SEQ_ID_CLKSYN_CNTL_2, sr15);
1500 WSeq(ba, SEQ_ID_RAMDAC_CNTL, sr18);
1501 WCrt(ba, CRT_ID_SCREEN_OFFSET, HDE);
1503 WCrt(ba, CRT_ID_MISC_1, (TEXT ? 0x05 : 0x35));
1505 test = RCrt(ba, CRT_ID_EXT_SYS_CNTL_2);
1509 WCrt(ba, CRT_ID_EXT_SYS_CNTL_2, test);
1536 WCrt(ba, CRT_ID_EXT_SYS_CNTL_1, cr50);
1540 WAttr(ba, ACT_ID_ATTR_MODE_CNTL, (TEXT ? 0x08 : 0x41));
1542 WAttr(ba, ACT_ID_COLOR_PLANE_ENA,
1563 WAttr(ba, 0x33, 0);
1566 cv3d_gfx_on_off(0, ba);
1641 * ba = boardaddr
1644 cv3dscreen(int toggle, volatile void *ba)
1646 *((volatile short *)(ba)) = (toggle & 1);
1651 /* ba= registerbase */
1653 cv3d_gfx_on_off(int toggle, volatile void *ba)
1660 r = RSeq(ba, SEQ_ID_CLOCKING_MODE);
1663 WSeq(ba, SEQ_ID_CLOCKING_MODE, r | toggle);
1681 volatile void *ba = gp->g_regkva;
1683 hi = RCrt(ba, CRT_ID_HWGC_ORIGIN_Y_HI);
1684 lo = RCrt(ba, CRT_ID_HWGC_ORIGIN_Y_LO);
1687 hi = RCrt(ba, CRT_ID_HWGC_ORIGIN_X_HI);
1688 lo = RCrt(ba, CRT_ID_HWGC_ORIGIN_X_LO);
1697 volatile void *ba = gp->g_regkva;
1727 WCrt(ba, CRT_ID_HWGC_ORIGIN_X_HI, (x >> 8));
1728 WCrt(ba, CRT_ID_HWGC_ORIGIN_X_LO, (x & 0xff));
1730 WCrt(ba, CRT_ID_HWGC_ORIGIN_Y_LO, (y & 0xff));
1731 WCrt(ba, CRT_ID_HWGC_DSTART_X, xoff);
1732 WCrt(ba, CRT_ID_HWGC_DSTART_Y, yoff);
1733 WCrt(ba, CRT_ID_HWGC_ORIGIN_Y_HI, (y >> 8));
1747 volatile void *ba, fb;
1749 ba = gp->g_regkva;
1753 info->enable = RCrt(ba, CRT_ID_HWGC_MODE) & 0x01;
1795 volatile void *ba = gp->g_regkva;
1806 test = RCrt(ba, CRT_ID_HWGC_MODE);
1811 moveb %1@(0x3d5),%0" : "=r" (test) : "a" (ba));
1814 WCrt (ba, CRT_ID_HWGC_FG_STACK, 0);
1816 hwc = ba + CRT_ADDRESS_W;
1821 test = RCrt(ba, CRT_ID_HWGC_MODE);
1826 moveb %1@(0x3d5),%0" : "=r" (test) : "a" (ba));
1830 WCrt (ba, CRT_ID_HWGC_BG_STACK, 0x1);
1834 WCrt (ba, CRT_ID_HWGC_BG_STACK, 0xff);
1840 WCrt (ba, CRT_ID_HWGC_START_AD_HI, (test >> 8));
1841 WCrt (ba, CRT_ID_HWGC_START_AD_LO, (test & 0xff));
1843 WCrt (ba, CRT_ID_HWGC_DSTART_X , 0);
1844 WCrt (ba, CRT_ID_HWGC_DSTART_Y , 0);
1846 WCrt (ba, CRT_ID_EXT_DAC_CNTL, 0x10); /* Cursor X11 Mode */
1852 WCrt (ba, CRT_ID_EXT_DAC_CNTL, 0x00); /* Cursor Windoze Mode */
1854 WCrt (ba, CRT_ID_HWGC_MODE, 0x01);
1863 #define VerticalRetraceWait(ba) \
1865 while (vgar(ba, GREG_INPUT_STATUS1_R) == 0x00) ; \
1866 while ((vgar(ba, GREG_INPUT_STATUS1_R) & 0x08) == 0x08) ; \
1867 while ((vgar(ba, GREG_INPUT_STATUS1_R) & 0x08) == 0x00) ; \
1874 volatile void *ba, fb;
1877 ba = gp->g_regkva;
1893 WCrt (ba, CRT_ID_HWGC_MODE, 0x00);
1915 VerticalRetraceWait(ba);
1917 WCrt (ba
1918 WCrt (ba, CRT_ID_HWGC_ORIGIN_X_LO, 0xff);
1919 WCrt (ba, CRT_ID_HWGC_ORIGIN_Y_LO, 0xff);
1920 WCrt (ba, CRT_ID_HWGC_DSTART_X, 0x3f);
1921 WCrt (ba, CRT_ID_HWGC_DSTART_Y, 0x3f);
1922 WCrt (ba, CRT_ID_HWGC_ORIGIN_Y_HI, 0x7);
1940 VerticalRetraceWait(ba);
2044 VerticalRetraceWait(ba);
2052 test = RCrt(ba, CRT_ID_HWGC_MODE);
2058 WCrt (ba, CRT_ID_HWGC_FG_STACK, 0);
2059 hwc = ba + CRT_ADDRESS_W;
2064 WCrt (ba, CRT_ID_HWGC_FG_STACK, 0);
2065 hwc = ba + CRT_ADDRESS_W;
2071 test = RCrt(ba, CRT_ID_HWGC_MODE);
2075 WCrt (ba, CRT_ID_HWGC_BG_STACK, 1);
2076 hwc = ba + CRT_ADDRESS_W;
2081 WCrt (ba, CRT_ID_HWGC_BG_STACK, 0xff);
2082 hwc = ba + CRT_ADDRESS_W;
2087 WCrt (ba, CRT_ID_HWGC_BG_STACK, 0xff);
2088 hwc = ba + CRT_ADDRESS_W;
2099 /* WCrt(ba, CRT_ID_HWGC_MODE, 0x01); */
2101 WCrt(ba, CRT_ID_HWGC_MODE, 0x00);
2134 volatile void *ba;
2140 ba = gp->g_regkva;
2144 /*WCrt(ba, CRT_ID_CURSOR_START, | 0x20);*/
2154 /*WCrt(ba, CRT_ID_CURSOR_START, | 0x20);*/
2158 WCrt(ba, CRT_ID_CURSOR_LOC_LOW, offs & 0xff);
2159 WCrt(ba, CRT_ID_CURSOR_LOC_HIGH, offs >> 8);
Indexes created Sat Oct 11 19:10:01 GMT 2025