Lines Matching defs:smc
29 * SMC 91C90 Single-Chip Ethernet Controller
202 es_dump_smcregs(const char *where, union smcregs *smc)
204 u_short cur_bank = smc->b0.bsr & BSR_MASK;
206 printf("SMC registers %p from %s bank %04x\n", smc, where,
207 smc->b0.bsr);
208 smc->b0.bsr = BSR_BANK0;
210 SWAP(smc->b0.tcr), SWAP(smc->b0.ephsr), SWAP(smc->b0.rcr),
211 SWAP(smc->b0.ecr), SWAP(smc->b0.mir), SWAP(smc->b0.mcr));
212 smc->b1.bsr = BSR_BANK1;
214 SWAP(smc->b1.cr), SWAP(smc->b1.bar), smc->b1.iar[0], smc->b1.iar[1],
215 smc->b1.iar[2], smc->b1.gpr, SWAP(smc->b1.ctr));
216 smc->b2.bsr = BSR_BANK2;
218 SWAP(smc->b2.mmucr), smc->b2.pnr, smc->b2.arr, smc->b2.fifo,
219 SWAP(smc->b2.ptr));
220 printf(" DATA %04x %04x IST %02x MSK %02x\n", smc->b2.data,
221 smc->b2.datax, smc->b2.ist, smc->b2.msk);
222 smc->b3.bsr = BSR_BANK3;
224 smc->b3.mt[0], smc->b3.mt[1], smc->b3.mt[2], smc->b3.mt[3]);
225 smc->b3.bsr = cur_bank;
232 union smcregs *smc = sc->sc_base;
237 smc->b2.bsr = BSR_BANK2;
238 smc->b2.msk = 0;
243 smc->b0.bsr = BSR_BANK0;
244 smc->b0.rcr = 0;
245 smc->b0.tcr = 0;
257 union smcregs *smc = sc->sc_base;
264 es_dump_smcregs("esinit", smc);
266 smc->b0.bsr = BSR_BANK0; /* Select bank 0 */
267 smc->b0.rcr = RCR_EPH_RST;
268 smc->b0.rcr = 0;
269 smc->b3.bsr = BSR_BANK3; /* Select bank 3 */
270 smc->b3.mt[0] = 0; /* clear Multicast table */
271 smc->b3.mt[1] = 0;
272 smc->b3.mt[2] = 0;
273 smc->b3.mt[3] = 0;
275 smc->b1.bsr = BSR_BANK1; /* Select bank 1 */
276 smc->b1.cr = CR_RAM32K | CR_NO_WAIT_ST | CR_SET_SQLCH;
277 smc->b1.ctr = CTR_AUTO_RLSE | CTR_TE_ENA;
278 smc->b1.iar[0] = *((const unsigned short *) &CLLADDR(ifp->if_sadl)[0]);
279 smc->b1.iar[1] = *((const unsigned short *) &CLLADDR(ifp->if_sadl)[2]);
280 smc->b1.iar[2] = *((const unsigned short *) &CLLADDR(ifp->if_sadl)[4]);
281 smc->b2.bsr = BSR_BANK2; /* Select bank 2 */
282 smc->b2.mmucr = MMUCR_RESET;
283 smc->b0.bsr = BSR_BANK0; /* Select bank 0 */
284 smc->b0.mcr = SWAP(0x0020); /* reserve 8K for transmit buffers */
285 smc->b0.tcr = TCR_PAD_EN | (TCR_TXENA + TCR_MON_CSN);
286 smc->b0.rcr = RCR_FILT_CAR | RCR_STRIP_CRC | RCR_RXEN | RCR_ALLMUL;
288 smc->b2.bsr = BSR_BANK2; /* Select bank 2 */
289 smc->b2.msk = sc->sc_intctl = MSK_RX_OVRN | MSK_RX | MSK_EPHINT;
307 union smcregs *smc;
310 smc = sc->sc_base;
312 while ((smc->b2.bsr & BSR_MASK) != BSR_BANK2 &&
315 smc->b2.bsr);
316 smc->b2.bsr = BSR_BANK2;
319 intsts = smc->b2.ist;
320 intact = smc->b2.msk & intsts;
328 device_xname(sc->sc_dev), intsts, smc->b2.msk);
337 smc->b2.msk = 0;
341 smc->b2.ist, smc->b2.ist, smc->b2.pnr, smc->b2.arr,
342 smc->b2.fifo);
351 if ((smc->b2.arr & ARR_FAILED) == 0) {
355 printf (" arr %02x\n", smc->b2.arr);
357 save_pnr = smc->b2.pnr;
358 smc->b2.pnr = smc->b2.arr;
359 smc->b2.mmucr = MMUCR_RLSPKT;
360 while (smc->b2.mmucr & MMUCR_BUSY)
362 smc->b2.pnr = save_pnr;
372 while ((smc->b2.bsr & BSR_MASK) != BSR_BANK2) {
374 smc->b2.bsr);
375 smc->b2.bsr = BSR_BANK2;
378 while ((smc->b2.fifo & FIFO_REMPTY) == 0) {
382 while ((smc->b2.bsr & BSR_MASK) != BSR_BANK2) {
384 smc->b2.bsr);
385 smc->b2.bsr = BSR_BANK2;
391 smc->b2.ist = ACK_RX_OVRN;
392 printf ("->%02x\n", smc->b2.ist);
403 smc->b2.ist = ACK_TX_EMPTY;
409 smc->b2.ist, sc->sc_intctl, smc->b2.pnr,
410 smc->b2.arr);
412 if (smc->b2.ist & IST_TX) {
418 smc->b0.bsr = BSR_BANK0;
419 ecr = smc->b0.ecr; /* Get error counters */
423 smc->b2.bsr = BSR_BANK2;
425 smc->b2.mmucr = MMUCR_RESET_TX; /* XXX reset TX FIFO */
437 printf ("->%02x\n", smc->b2.ist);
445 smc->b0.bsr = BSR_BANK0;
446 ephsr = smc->b0.ephsr; /* get EPHSR */
448 tcr = smc->b0.tcr; /* and TCR */
449 smc->b2.bsr = BSR_BANK2;
450 save_ptr = smc->b2.ptr;
451 save_pnr = smc->b2.pnr;
452 tx_pnr = smc->b2.fifo >> 8; /* pktno from completion fifo */
453 smc->b2.pnr = tx_pnr; /* set TX packet number */
454 smc->b2.ptr = PTR_READ; /* point to status word */
457 device_xname(sc->sc_dev), smc->b2.ist,
459 printf(" Status %04x", smc->b2.data);
462 if ((smc->b2.data & EPHSR_TX_SUC) == 0 && (tcr & TCR_TXENA) == 0) {
468 smc->b2.mmucr = MMUCR_ENQ_TX;
469 smc->b0.bsr = BSR_BANK0;
470 smc->b0.tcr |= TCR_TXENA;
471 smc->b2.bsr = BSR_BANK2;
487 if (smc->b2.ist & IST_TX_EMPTY) {
488 smc->b2.mmucr = MMUCR_RESET_TX;
497 smc->b2.pnr = save_pnr;
498 smc->b2.ptr = save_ptr;
499 smc->b2.ist = ACK_TX;
501 if ((smc->b2.fifo & FIFO_TEMPTY) == 0 && n++ < 32) {
504 device_xname(sc->sc_dev), n, tx_pnr, smc->b2.ist, smc->b2.fifo);
505 smc->w2.istmsk = ACK_TX << 8;
506 printf(" %04x\n", smc->b2.fifo);
508 if (tx_pnr != (smc->b2.fifo >> 8))
519 while ((smc->b2.bsr & BSR_MASK) != BSR_BANK2) {
521 smc->b2.bsr);
522 smc->b2.bsr = BSR_BANK2;
525 smc->b2.msk = sc->sc_intctl;
539 union smcregs *smc = sc->sc_base;
561 smc->b2.fifo);
566 while ((smc->b2.bsr & BSR_MASK) != BSR_BANK2) {
568 smc->b2.bsr);
569 smc->b2.bsr = BSR_BANK2;
572 data = (volatile u_short *)&smc->b2.data;
573 smc->b2.ptr = PTR_RCV | PTR_AUTOINCR | PTR_READ | SWAP(0x0002);
574 (void) smc->b2.mmucr;
577 printf ("->%04x", smc->b2.fifo);
585 smc->b2.ptr = PTR_RCV | (PTR_AUTOINCR + PTR_READ) | SWAP(0x0000);
586 (void) smc->b2.mmucr;
595 device_xname(sc->sc_dev), pktctlw, pktlen, len, smc->b2.bsr);
598 if ((smc->b2.bsr & BSR_MASK) != BSR_BANK2)
601 smc->b2.bsr = BSR_BANK2;
602 smc->b2.mmucr = MMUCR_REMRLS_RX;
603 while (smc->b2.mmucr & MMUCR_BUSY)
632 smc->b2.mmucr = MMUCR_REMRLS_RX;
633 while (smc->b2.mmucr & MMUCR_BUSY)
642 smc->b2.fifo);
659 smc->b2.fifo);
715 smc->b2.mmucr = MMUCR_REMRLS_RX;
716 while (smc->b2.mmucr & MMUCR_BUSY)
743 union smcregs *smc = sc->sc_base;
769 while ((smc->b2.bsr & BSR_MASK) != BSR_BANK2) {
771 smc->b2.bsr);
772 smc->b2.bsr = BSR_BANK2;
781 * and see if the SMC 91C90 can accept it.
799 smc->b2.mmucr = MMUCR_ALLOC | (pktlen & 0x0700);
801 if ((smc->b2.arr & ARR_FAILED) == 0)
803 if (smc->b2.arr & ARR_FAILED) {
809 active_pnr = smc->b2.pnr = smc->b2.arr;
812 while ((smc->b2.bsr & BSR_MASK) != BSR_BANK2) {
814 smc->b2.bsr);
815 smc->b2.bsr = BSR_BANK2;
818 smc->b2.ptr = PTR_AUTOINCR;
819 (void) smc->b2.mmucr;
820 data = (volatile u_short *)&smc->b2.data;
824 while ((smc->b2.bsr & BSR_MASK) != BSR_BANK2) {
826 smc->b2.bsr);
827 smc->b2.bsr = BSR_BANK2;
859 while ((smc->b2.bsr & BSR_MASK) != BSR_BANK2) {
861 smc->b2.bsr);
862 smc->b2.bsr = BSR_BANK2;
864 start_ptr = SWAP(smc->b2.ptr); /* save PTR before copy */
871 end_ptr = SWAP(smc->b2.ptr); /* save PTR after copy */
894 while ((smc->b2.bsr & BSR_MASK) != BSR_BANK2) {
906 device_xname(sc->sc_dev), smc->b2.bsr);
908 smc->b2.bsr = BSR_BANK2;
912 start_ptr, end_ptr, SWAP(smc->b2.ptr));
920 smc->b2.mmucr = MMUCR_ENQ_TX;
921 if (smc->b2.pnr != active_pnr)
923 device_xname(sc->sc_dev), active_pnr, smc->b2.pnr);
931 smc->b2.msk = sc->sc_intctl;
933 while ((smc->b2.bsr & BSR_MASK) != BSR_BANK2) {
935 smc->b2.bsr);
936 smc->b2.bsr = BSR_BANK2;
Indexes created Tue Sep 30 11:09:46 GMT 2025