Lines Matching refs:u_short
34 volatile u_short tcr; /* Transmit Control Register */
35 volatile u_short ephsr; /* EPH Status Register */
36 volatile u_short rcr; /* Receive Control Register */
37 volatile u_short ecr; /* Counter Register */
38 volatile u_short mir; /* Memory Information Register */
39 volatile u_short mcr; /* Memory Configuration Register */
40 volatile u_short resv;
41 volatile u_short bsr; /* Bank Select Register */
44 volatile u_short cr; /* Configuration Register */
45 volatile u_short bar; /* Base Address Register */
46 volatile u_short iar[3]; /* Individual Address Registers */
47 volatile u_short gpr; /* General Purpose Register */
48 volatile u_short ctr; /* Control Register */
49 volatile u_short bsr; /* Bank Select Register */
52 volatile u_short mmucr; /* MMU Command Register */
55 volatile u_short fifo; /* FIFO Ports Register */
56 volatile u_short ptr; /* Pointer Register */
57 volatile u_short data; /* Data Register */
58 volatile u_short datax; /* Data Register (2nd mapping) */
61 volatile u_short bsr; /* Bank Select Register */
64 volatile u_short mt[4]; /* Multicast Table */
65 volatile u_short resv[3];
66 volatile u_short bsr; /* Bank Select Register */
69 * Bank 2 registers defined as u_short fields
72 volatile u_short mmucr; /* MMU Command Register */
73 volatile u_short pnrarr;/* Packet Number/Allocation Result */
74 volatile u_short fifo; /* FIFO Ports Register */
75 volatile u_short ptr; /* Pointer Register */
76 volatile u_short data; /* Data Register */
77 volatile u_short datax; /* Data Register (2nd mapping) */
78 volatile u_short istmsk;/* Interrupt Status/Mask Register */
79 volatile u_short bsr; /* Bank Select Register */
Indexes created Sun Oct 19 02:09:48 GMT 2025