Lines Matching defs:asr
189 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \
200 u_char asr;
258 int count, asr, s;
270 GET_SBIC_asr(regs, asr);
271 if (asr & SBIC_ASR_DBR) {
272 printf("sbic_save_ptrs: asr %02x canceled!\n", asr);
277 } while (asr & (SBIC_ASR_BSY|SBIC_ASR_CIP));
294 acb->sc_dmacmd, asr);
711 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n",
729 u_char csr, asr;
731 GET_SBIC_asr(regs, asr);
734 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n",
735 device_xname(dev->sc_dev), where, csr, asr);
752 while (asr & SBIC_ASR_DBR) {
755 GET_SBIC_data(regs, asr);
757 device_xname(dev->sc_dev), where, asr);
758 GET_SBIC_asr(regs, asr);
759 if (asr & SBIC_ASR_DBR) /* Not the read direction, then */
760 SET_SBIC_data(regs, asr);
761 GET_SBIC_asr(regs, asr);
768 GET_SBIC_asr(regs, asr);
769 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) {
772 printf("%s: sbicabort - asr %x, trying to reset\n", device_xname(dev->sc_dev), asr);
781 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0);
783 CSR_TRACE('a',csr,asr,0);
968 u_char asr, csr, id;
997 GET_SBIC_asr(regs, asr);
998 if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) {
1000 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/
1016 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0);
1017 if (asr & SBIC_ASR_LCI) {
1020 printf("sbicselectbus: late LCI asr %02x\n", asr);
1026 CSR_TRACE('s',csr,asr,target);
1031 printf("sbicselectbus: reselected asr %02x\n", asr);
1034 sbicnextstate(dev, csr, asr);
1128 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0);
1130 CSR_TRACE('y',csr,asr,target);
1181 u_char orig_csr, asr, *buf;
1204 GET_SBIC_asr (regs, asr);
1205 while ((asr & SBIC_ASR_DBR) == 0) {
1206 if ((asr & SBIC_ASR_INT) || --wait < 0) {
1210 len, asr, wait);
1215 GET_SBIC_asr (regs, asr);
1234 u_char orig_csr, csr, asr;
1255 GET_SBIC_asr (regs, asr);
1256 if ((asr & SBIC_ASR_PE)) {
1259 len, asr, wait);
1266 while ((asr & SBIC_ASR_DBR) == 0) {
1267 if ((asr & SBIC_ASR_INT) || --wait < 0) {
1274 len, asr, wait);
1280 if (!(asr & SBIC_ASR_BSY)) {
1283 CSR_TRACE('<',csr,asr,len);
1284 QPRINTF(("[CSR%02xASR%02x]", csr, asr));
1288 GET_SBIC_asr (regs, asr);
1292 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/
1318 u_char phase, csr, asr;
1378 GET_SBIC_asr (regs, asr);
1380 CSR_TRACE('I',csr,asr,target);
1381 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr));
1418 GET_SBIC_asr(regs, asr);
1419 CSR_TRACE('I',csr,asr,target);
1420 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP))
1421 printf("next: cmd sent asr %02x, csr %02x\n",
1422 asr, csr);
1485 i = sbicnextstate(dev, csr, asr);
1492 GET_SBIC_asr(regs, asr);
1495 while (asr & SBIC_ASR_BSY){
1496 if (asr & SBIC_ASR_DBR) {
1497 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n",
1498 csr,asr);
1506 GET_SBIC_asr(regs, asr);
1507 if (asr & SBIC_ASR_DBR) /* Wants us to write */
1510 GET_SBIC_asr(regs, asr);
1516 if (asr & SBIC_ASR_LCI) {
1529 CSR_TRACE('I',csr,asr,0xff);
1561 u_char phase, asr, csr;
1576 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0);
1577 __USE(asr);
1579 CSR_TRACE('f',csr,asr,target);
1606 u_char csr, asr, *addr;
1772 * Hmm - this isn't right: asr and csr haven't been set yet.
1774 debug_asr = asr;
1783 GET_SBIC_asr(regs, asr);
1786 CSR_TRACE('g',csr,asr,dev->target);
1793 i = sbicnextstate(dev, csr, asr);
1796 GET_SBIC_asr(regs, asr);
1798 debug_asr = asr;
1800 if (asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n",
1801 asr,csr);
1803 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI));
1805 CSR_TRACE('g',csr,asr,i<<4);
1821 u_char asr, csr;
1829 GET_SBIC_asr (regs, asr);
1830 if ((asr & SBIC_ASR_INT) == 0)
1836 CSR_TRACE('i',csr,asr,dev->target);
1843 i = sbicnextstate(dev, csr, asr);
1846 GET_SBIC_asr(regs, asr);
1848 debug_asr = asr;
1851 if (asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n",
1852 asr,csr);
1855 asr & (SBIC_ASR_INT|SBIC_ASR_LCI));
1856 CSR_TRACE('i',csr,asr,i<<4);
1868 u_char asr, csr;
1875 GET_SBIC_asr (regs, asr);
1877 debug_asr = asr;
1880 CSR_TRACE('p',csr,asr,dev->target);
1887 i = sbicnextstate(dev, csr, asr);
1890 GET_SBIC_asr(regs, asr);
1892 while (asr & SBIC_ASR_BSY){
1893 if (asr & SBIC_ASR_DBR) {
1894 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n",
1895 csr,asr);
1903 GET_SBIC_asr(regs, asr);
1904 if (asr & SBIC_ASR_DBR) /* Wants us to write */
1907 GET_SBIC_asr(regs, asr);
1910 if (asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n",
1911 asr,csr);
1915 CSR_TRACE('p',csr,asr,i<<4);
1929 u_char asr, csr, *tmpaddr;
1936 GET_SBIC_asr(regs, asr);
1939 printf("sbicmsgin asr=%02x\n", asr);
1952 GET_SBIC_asr(regs, asr);
1954 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n",
1955 csr, asr));
1958 CSR_TRACE('m',csr,asr,*tmpaddr);
1966 CSR_TRACE('X',csr,asr,dev->target);
1970 GET_SBIC_asr(regs, asr);
1973 CSR_TRACE('X',csr,asr,dev->target);
1975 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr);
1980 printf("sbicmsgin: got %02x csr %02x asr %02x\n",
1981 *tmpaddr, csr, asr);
1984 if (asr & SBIC_ASR_PE) {
1990 GET_SBIC_asr(regs, asr);
1994 if (!(asr & SBIC_ASR_LCI))
2000 while ((asr & SBIC_ASR_BSY) &&
2001 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT))
2002 GET_SBIC_asr(regs, asr);
2003 if (asr & SBIC_ASR_DBR)
2006 CSR_TRACE('e',csr,asr,dev->target);
2008 sbicnextstate(dev, csr, asr);
2024 GET_SBIC_asr(regs, asr);
2026 CSR_TRACE('X',csr,asr,dev->target);
2027 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n",
2028 csr, asr));
2041 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n",
2042 csr, asr, dev->sc_msg[0]);
2117 GET_SBIC_asr(regs, asr);
2118 if (asr & SBIC_ASR_BSY)
2129 GET_SBIC_asr(regs, asr);
2131 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr));
2133 CSR_TRACE('x',csr,asr,*tmpaddr);
2137 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n",
2138 asr, csr, recvlen));
2166 GET_SBIC_asr(regs, asr);
2168 CSR_TRACE('X',csr,asr,dev->target);
2169 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n",
2170 csr, asr, recvlen));
2181 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr));
2197 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr)
2211 QPRINTF(("next[%02x,%02x]",asr,csr));
2288 printf("sbicnextstate:xfer count %d asr%x csr%x\n",
2289 acb->sc_kv.dc_count, asr, csr);
2312 printf("sbicnextstate:xfer count %d asr%x csr%x\n",
2313 acb->sc_kv.dc_count, asr, csr);
2377 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP))
2378 printf("next: REJECT sent asr %02x\n", asr);
2416 CSR_TRACE('r',csr,asr,newtarget);
2420 GET_SBIC_asr(regs, asr);
2421 if (asr & SBIC_ASR_INT)
2426 if ((asr & SBIC_ASR_INT) == 0) {
2429 printf("RSLT_NI - no IFFY message? asr %x\n", asr);
2433 CSR_TRACE('n',csr,asr,newtarget);
2501 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr);
2621 u_char csr, asr;
2623 GET_SBIC_asr(debug_sbic_regs,asr);
2625 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n",
2630 debug_asr, debug_csr, asr, csr);
2637 int s, asr;
2644 GET_SBIC_asr(dev->sc_sbic, asr);
2645 if (asr & SBIC_ASR_INT) {
2648 debug_asr, debug_csr, asr);
2688 u_char csr, asr;
2700 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn);
2785 if (csr_trace[i].asr & SBIC_ASR_INT)
2787 if (csr_trace[i].asr & SBIC_ASR_LCI)
2789 if (csr_trace[i].asr & SBIC_ASR_BSY)
2791 if (csr_trace[i].asr & SBIC_ASR_CIP)
2797 GET_SBIC_asr(regs, asr);
2798 if ((asr & SBIC_ASR_INT) == 0)
2802 printf("%s@%p regs %p/%p asr %x csr %x\n", device_xname(dev->sc_dev),
2803 dev, regs.sbic_asr_p, regs.sbic_value_p, asr, csr);
Indexes created Tue Sep 30 11:09:46 GMT 2025