Cross Reference: /src/sys/arch/arm/acpi/acpi_pci_layerscape

Lines Matching defs:pcie
33  * NXP Layerscape PCIe Gen4 controller (not ECAM compliant)
85 acpi_pci_layerscape_gen4_ccsr_setpage(struct acpi_pci_layerscape_gen4 *pcie, u_int page_index)
89 	val = bus_space_read_4(pcie->bst, pcie->bsh, PAB_CTRL);
92 	bus_space_write_4(pcie->bst, pcie->bsh, PAB_CTRL, val);
96 acpi_pci_layerscape_gen4_ccsr_read4(struct acpi_pci_layerscape_gen4 *pcie, bus_size_t reg)
102 	acpi_pci_layerscape_gen4_ccsr_setpage(pcie, page_index);
103 	return bus_space_read_4(pcie->bst, pcie->bsh, page_addr);
107 acpi_pci_layerscape_gen4_ccsr_write4(struct acpi_pci_layerscape_gen4 *pcie,
114 	acpi_pci_layerscape_gen4_ccsr_setpage(pcie, page_index);
115 	bus_space_write_4(pcie->bst, pcie->bsh, page_addr, data);
119 acpi_pci_layerscape_gen4_select_target(struct acpi_pci_layerscape_gen4 *pcie,
129 	acpi_pci_layerscape_gen4_ccsr_write4(pcie, PAB_AXI_AMAP_PEX_WIN_L(0), target);
130 	acpi_pci_layerscape_gen4_ccsr_write4(pcie, PAB_AXI_AMAP_PEX_WIN_H(0), 0);
154 	struct acpi_pci_layerscape_gen4 *pcie = ap->ap_conf_priv;
164 	mutex_enter(&pcie->lock);
166 	if (pcie->rev == 0x10 && reg == PCI_ID_REG)
167 		bus_space_write_4(pcie->bst, pcie->bsh, LUT_BASE + LUT_GCR, 0);
170 		*data = acpi_pci_layerscape_gen4_ccsr_read4(pcie, reg);
172 		acpi_pci_layerscape_gen4_select_target(pcie, pc, tag);
173 		*data = bus_space_read_4(pcie->bst, pcie->win_bsh, reg);
176 	if (pcie->rev == 0x10 && reg == PCI_ID_REG)
177 		bus_space_write_4(pcie->bst, pcie->bsh, LUT_BASE + LUT_GCR, LUT_GCR_RRE);
179 	mutex_exit(&pcie->lock);
188 	struct acpi_pci_layerscape_gen4 *pcie = ap->ap_conf_priv;
196 	mutex_enter(&pcie->lock);
199 		acpi_pci_layerscape_gen4_ccsr_write4(pcie, reg, data);
201 		acpi_pci_layerscape_gen4_select_target(pcie, pc, tag);
202 		bus_space_write_4(pcie->bst, pcie->win_bsh, reg, data);
205 	mutex_exit(&pcie->lock);
241 	struct acpi_pci_layerscape_gen4 *pcie;
279 	pcie = kmem_alloc(sizeof(*pcie), KM_SLEEP);
280 	pcie->bst = ap->ap_bst;
281 	pcie->bsh = bsh;
282 	mutex_init(&pcie->lock, MUTEX_DEFAULT, IPL_HIGH);
285 	    BUS_SPACE_MAP_NONPOSTED, &pcie->win_bsh);
289 	const pcireg_t cr = bus_space_read_4(pcie->bst, pcie->bsh, PCI_CLASS_REG);
290 	pcie->rev = PCI_REVISION(cr);
294 	ap->ap_conf_priv = pcie;
297 	    "PCIe segment %lu: Layerscape Gen4 rev. %#x found at %#lx-%#lx\n",
298 	    seg, pcie->rev, mem->ar_base, mem->ar_base + mem->ar_length - 1);
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