Lines Matching refs:clk
17 #include <dev/clk/clk_backend.h>
29 static struct clk *cycv_clkmgr_clock_decode(device_t, int, const void *,
36 static struct clk *cycv_clkmgr_clock_get(void *, const char *);
37 static void cycv_clkmgr_clock_put(void *, struct clk *);
38 static u_int cycv_clkmgr_clock_get_rate(void *, struct clk *);
39 static int cycv_clkmgr_clock_set_rate(void *, struct clk *, u_int);
40 static int cycv_clkmgr_clock_enable(void *, struct clk *);
41 static int cycv_clkmgr_clock_disable(void *, struct clk *);
42 static int cycv_clkmgr_clock_set_parent(void *, struct clk *, struct clk *);
43 static struct clk *cycv_clkmgr_clock_get_parent(void *, struct clk *);
57 struct clk base;
115 { .compat = "altr,clk-mgr" },
219 { .compat = "altr,socfpga-perip-clk", .value = CYCV_CLK_TYPE_PERIP },
220 { .compat = "altr,socfpga-gate-clk", .value = CYCV_CLK_TYPE_PERIP },
227 struct cycv_clk *clk = &sc->sc_clocks[clkno];
232 clk->base.domain = &sc->sc_clkdom;
233 clk->base.name = fdtbus_get_string(handle, "name");
234 clk->base.flags = 0;
236 clk->id = handle;
237 clk->parent = NULL;
238 clk->parent_id = 0;
239 clk->refcnt = 0;
245 clk->type = dce->value;
247 if (clk->type == CYCV_CLK_TYPE_FIXED) {
249 &clk->u.fixed_freq) == 0) {
252 } else if (clk->type == CYCV_CLK_TYPE_PLL) {
253 if (fdtbus_get_reg(handle, 0, &clk->u.pll_addr, NULL) != 0)
256 } else if (clk->type == CYCV_CLK_TYPE_PERIP) {
258 &clk->u.fixed_div) == 0) {
259 clk->type = CYCV_CLK_TYPE_FIXED_DIV;
260 } else if (fdtbus_get_reg(handle, 0, &clk->u.div.addr, NULL) ==
262 clk->type = CYCV_CLK_TYPE_DIV;
263 clk->u.div.shift = 0;
264 clk->u.div.mask = 0xff;
270 clk->type = CYCV_CLK_TYPE_DIV;
271 clk->u.div.addr = of_decode_int(buf);
272 clk->u.div.shift = of_decode_int(buf + 4);
273 clk->u.div.mask = ((1 << of_decode_int(buf + 8)) - 1) <<
274 clk->u.div.shift;
277 clk->type = CYCV_CLK_TYPE_FIXED_DIV;
278 clk->u.fixed_div = 1;
284 if ((buf = fdtbus_get_prop(handle, "clk-gate", &len)) != NULL) {
285 clk->gate_addr = of_decode_int(buf);
286 clk->gate_shift = of_decode_int(buf + 4);
292 clk->parent_id =
296 clk->flags = flags;
304 clk->base.name, handle);
369 cycv_clkmgr_clock_print(struct cycv_clkmgr_softc *sc, struct cycv_clk *clk)
375 aprint_debug("clock %s, id %d, frequency %uHz:\n", clk->base.name,
376 clk->id, cycv_clkmgr_clock_get_rate(sc, &clk->base));
377 if (clk->parent != NULL)
378 aprint_debug("parent: %s", clk->parent->base.name);
380 aprint_debug("parent_id: %d", clk->parent_id);
381 aprint_debug(", flags: %d\n", clk->flags);
382 switch (clk->type) {
384 tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, clk->u.pll_addr);
390 aprint_debug(" Fixed frequency = %u\n", clk->u.fixed_freq);
393 aprint_debug(" Fixed divisor = %u\n", clk->u.fixed_div);
396 tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, clk->u.div.addr);
397 tmp = (tmp & clk->u.div.mask) >> clk->u.div.shift;
398 if (__SHIFTOUT_MASK(clk->u.div.mask) > 0xf)
409 if (clk->flags & CYCV_CLK_FLAG_HAVE_GATE) {
410 tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, clk->gate_addr);
411 tmp &= (1 << clk->gate_shift);
418 static struct clk *
423 struct cycv_clk *clk;
430 clk = cycv_clkmgr_clock_lookup_by_id(sc, cc_phandle);
432 return clk == NULL? NULL : &clk->base;
435 static struct clk *
446 cycv_clkmgr_clock_put(void *priv, struct clk *clk)
452 cycv_clkmgr_clock_get_rate(void *priv, struct clk *base_clk)
455 struct cycv_clk *clk = (struct cycv_clk *) base_clk;
462 if (clk->type == CYCV_CLK_TYPE_FIXED)
463 return clk->u.fixed_freq;
469 clk->base.name);
474 if (strncmp(clk->base.name, "mpuclk@", strlen("mpuclk@")) == 0)
476 else if (strncmp(clk->base.name, "mainclk@", strlen("mainclk@")) == 0)
478 else if (strncmp(clk->base.name, "dbgatclk@", strlen("dbgatclk@")) == 0)
481 switch (clk->type) {
483 return parent_rate / clk->u.fixed_div;
487 clk->u.div.addr);
488 divisor = (divisor & clk->u.div.mask) >> clk->u.div.shift;
489 if (__SHIFTOUT_MASK(clk->u.div.mask) > 0xf)
497 tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, clk->u.pll_addr);
504 aprint_debug_dev(sc->sc_dev, "unknown clock type %d\n", clk->type);
510 cycv_clkmgr_clock_set_rate(void *priv, struct clk *clk, u_int rate)
517 cycv_clkmgr_clock_set(void *priv, struct clk *base_clk, int val)
520 struct cycv_clk *clk = (struct cycv_clk *) base_clk;
522 if (clk->flags & CYCV_CLK_FLAG_HAVE_GATE) {
524 clk->gate_addr);
525 tmp &= ~(1 << clk->gate_shift);
526 tmp |= val << clk->gate_shift;
527 bus_space_write_4(sc->sc_bst, sc->sc_bsh, clk->gate_addr, tmp);
536 cycv_clkmgr_clock_enable(void *priv, struct clk *clk)
538 return cycv_clkmgr_clock_set(priv, clk, 1);
542 cycv_clkmgr_clock_disable(void *priv, struct clk *clk)
544 return cycv_clkmgr_clock_set(priv, clk, 0);
548 cycv_clkmgr_clock_set_parent(void *priv, struct clk *clk,
549 struct clk *clk_parent)
551 /* lookup clk in muxinfo table */
555 /* enact reparenting h/w wise, update clk->parent */
560 static struct clk *
561 cycv_clkmgr_clock_get_parent(void *priv, struct clk *base_clk)
564 struct cycv_clk *clk = (struct cycv_clk *) base_clk;
566 struct cycv_clk *parent = clk->parent;
573 if (clk->parent_id != 0) {
574 parent = cycv_clkmgr_clock_lookup_by_id(sc, clk->parent_id);
578 mux = cycv_clkmgr_get_mux_info(clk->base.name);
593 clk->base.name, parent_index);
601 clk->parent = parent;