Lines Matching refs:MESON_CLK_PLL_REG
185 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */
186 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */
187 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */
189 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */
190 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */
240 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(30)), /* enable */
241 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(8,0)), /* m */
242 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(13,9)), /* n */
243 MESON_CLK_PLL_REG(HHI_MPLL_CNTL2, __BITS(11,0)), /* frac */
244 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(31)), /* l */
245 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(29)), /* reset */
259 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(13,0)), /* sdm */
260 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BIT(15)), /* sdm_enable */
261 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(24,16)), /* n2 */
262 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(25)), /* ssen */
265 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */
266 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
267 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */
271 MESON_CLK_PLL_REG(HHI_MPLL_CNTL9, __BITS(13,0)), /* sdm */
272 MESON_CLK_PLL_REG(HHI_MPLL_CNTL9, __BIT(15)), /* sdm_enable */
273 MESON_CLK_PLL_REG(HHI_MPLL_CNTL9, __BITS(24,16)), /* n2 */
Indexes created Sat Oct 18 17:09:52 GMT 2025