Lines Matching defs:w0
332 uint32_t cs, tc, w0, w1, w2, w3, w4;
357 w0 = VPU_READ(sc, VIU_OSD2_BLK0_CFG_W0_REG);
358 w0 |= VIU_OSD_BLK_CFG_W0_RGB_EN;
359 w0 &= ~VIU_OSD_BLK_CFG_W0_TC_ALPHA_EN;
360 w0 &= ~VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE;
361 w0 &= ~VIU_OSD_BLK_CFG_W0_COLOR_MATRIX;
364 w0 |= __SHIFTIN(VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_32BPP,
366 w0 |= __SHIFTIN(VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_ARGB,
370 w0 |= __SHIFTIN(VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_24BPP,
372 w0 |= __SHIFTIN(VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_RGB,
376 w0 |= __SHIFTIN(VIU_OSD_BLK_CFG_W0_OSD_BLK_MODE_16BPP,
378 w0 |= __SHIFTIN(VIU_OSD_BLK_CFG_W0_COLOR_MATRIX_RGB565,
382 w0 |= VIU_OSD_BLK_CFG_W0_LITTLE_ENDIAN;
383 w0 &= ~VIU_OSD_BLK_CFG_W0_RPT_Y;
384 w0 &= ~VIU_OSD_BLK_CFG_W0_INTERP_CTRL;
386 w0 |= VIU_OSD_BLK_CFG_W0_INTERLACE_EN;
388 w0 &= ~VIU_OSD_BLK_CFG_W0_INTERLACE_EN;
390 VPU_WRITE(sc, VIU_OSD2_BLK0_CFG_W0_REG, w0);
Indexes created Sun Sep 28 16:09:52 GMT 2025