Lines Matching defs:CBUS_REG
42 #define CBUS_REG(x) ((x) << 2)
44 #define HHI_GP0_PLL_CNTL0 CBUS_REG(0x10)
45 #define HHI_GP0_PLL_CNTL1 CBUS_REG(0x11)
46 #define HHI_GP0_PLL_CNTL2 CBUS_REG(0x12)
47 #define HHI_GP0_PLL_CNTL3 CBUS_REG(0x13)
48 #define HHI_GP0_PLL_CNTL4 CBUS_REG(0x14)
49 #define HHI_GP0_PLL_CNTL5 CBUS_REG(0x15)
50 #define HHI_GP0_PLL_CNTL6 CBUS_REG(0x16)
51 #define HHI_GP1_PLL_CNTL0 CBUS_REG(0x18)
52 #define HHI_GP1_PLL_CNTL1 CBUS_REG(0x19)
53 #define HHI_PCIE_PLL_CNTL0 CBUS_REG(0x26)
63 #define HHI_PCIE_PLL_CNTL1 CBUS_REG(0x27)
66 #define HHI_PCIE_PLL_CNTL2 CBUS_REG(0x28)
73 #define HHI_PCIE_PLL_CNTL3 CBUS_REG(0x29)
83 #define HHI_PCIE_PLL_CNTL4 CBUS_REG(0x2a)
97 #define HHI_PCIE_PLL_CNTL5 CBUS_REG(0x2b)
113 #define HHI_HIFI_PLL_CNTL0 CBUS_REG(0x36)
114 #define HHI_HIFI_PLL_CNTL1 CBUS_REG(0x37)
115 #define HHI_HIFI_PLL_CNTL2 CBUS_REG(0x38)
116 #define HHI_HIFI_PLL_CNTL3 CBUS_REG(0x39)
117 #define HHI_HIFI_PLL_CNTL4 CBUS_REG(0x3a)
118 #define HHI_HIFI_PLL_CNTL5 CBUS_REG(0x3b)
119 #define HHI_HIFI_PLL_CNTL6 CBUS_REG(0x3c)
120 #define HHI_MEM_PD_REG0 CBUS_REG(0x40)
121 #define HHI_GCLK_MPEG0 CBUS_REG(0x50)
122 #define HHI_GCLK_MPEG1 CBUS_REG(0x51)
123 #define HHI_GCLK_MPEG2 CBUS_REG(0x52)
124 #define HHI_GCLK_OTHER CBUS_REG(0x54)
125 #define HHI_GCLK_OTHER2 CBUS_REG(0x55)
126 #define HHI_SYS_CPU_CLK_CNTL1 CBUS_REG(0x57)
127 #define HHI_MPEG_CLK_CNTL CBUS_REG(0x5d)
128 #define HHI_TS_CLK_CNTL CBUS_REG(0x64)
129 #define HHI_SYS_CPU_CLK_CNTL0 CBUS_REG(0x67)
130 #define HHI_VID_PLL_CLK_DIV CBUS_REG(0x68)
131 #define HHI_SYS_CPUB_CLK_CNTL1 CBUS_REG(0x80)
132 #define HHI_SYS_CPUB_CLK_CNTL CBUS_REG(0x82)
133 #define HHI_NAND_CLK_CNTL CBUS_REG(0x97)
134 #define HHI_SD_EMMC_CLK_CNTL CBUS_REG(0x99)
135 #define HHI_MPLL_CNTL0 CBUS_REG(0x9e)
136 #define HHI_MPLL_CNTL1 CBUS_REG(0x9f)
137 #define HHI_MPLL_CNTL2 CBUS_REG(0xa0)
138 #define HHI_MPLL_CNTL3 CBUS_REG(0xa1)
139 #define HHI_MPLL_CNTL4 CBUS_REG(0xa2)
140 #define HHI_MPLL_CNTL5 CBUS_REG(0xa3)
141 #define HHI_MPLL_CNTL6 CBUS_REG(0xa4)
142 #define HHI_MPLL_CNTL7 CBUS_REG(0xa5)
143 #define HHI_MPLL_CNTL8 CBUS_REG(0xa6)
144 #define HHI_FIX_PLL_CNTL0 CBUS_REG(0xa8)
145 #define HHI_FIX_PLL_CNTL1 CBUS_REG(0xa9)
146 #define HHI_FIX_PLL_CNTL2 CBUS_REG(0xaa)
147 #define HHI_FIX_PLL_CNTL3 CBUS_REG(0xab)
148 #define HHI_SYS_PLL_CNTL0 CBUS_REG(0xbd)
149 #define HHI_SYS_PLL_CNTL1 CBUS_REG(0xbe)
150 #define HHI_SYS_PLL_CNTL2 CBUS_REG(0xbf)
151 #define HHI_SYS_PLL_CNTL3 CBUS_REG(0xc0)
152 #define HHI_SYS_PLL_CNTL4 CBUS_REG(0xc1)
153 #define HHI_SYS_PLL_CNTL5 CBUS_REG(0xc2)
154 #define HHI_SYS_PLL_CNTL6 CBUS_REG(0xc3)
155 #define HHI_HDMI_PLL_CNTL0 CBUS_REG(0xc8)
156 #define HHI_HDMI_PLL_CNTL1 CBUS_REG(0xc9)
157 #define HHI_SYS1_PLL_CNTL0 CBUS_REG(0xe0)
158 #define HHI_SYS1_PLL_CNTL1 CBUS_REG(0xe1)
159 #define HHI_SYS1_PLL_CNTL2 CBUS_REG(0xe2)
160 #define HHI_SYS1_PLL_CNTL3 CBUS_REG(0xe3)
161 #define HHI_SYS1_PLL_CNTL4 CBUS_REG(0xe4)
162 #define HHI_SYS1_PLL_CNTL5 CBUS_REG(0xe5)
163 #define HHI_SYS1_PLL_CNTL6 CBUS_REG(0xe6)
1365 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(1), 0x00000000);
1366 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(2), 0x00000000);
1367 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(3), 0x48681c00);
1368 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(4), 0x88770290);
1369 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(5), 0x39272000);
Indexes created Tue Sep 30 20:09:53 GMT 2025