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Lines Matching refs:CLK_WRITE

1352 	CLK_WRITE(sc, clk->u.mux.reg, val & ~__BIT(11));
1360 CLK_WRITE(sc, reg_cntl0, val | MESON_PLL_CNTL_REG_RST);
1362 CLK_WRITE(sc, reg_cntl0, val & ~MESON_PLL_CNTL_REG_EN);
1365 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(1), 0x00000000);
1366 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(2), 0x00000000);
1367 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(3), 0x48681c00);
1368 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(4), 0x88770290);
1369 CLK_WRITE(sc, reg_cntl0 + CBUS_REG(5), 0x39272000);
1380 CLK_WRITE(sc, reg_cntl0, val);
1384 CLK_WRITE(sc, reg_cntl0, val | MESON_PLL_CNTL_REG_RST);
1386 CLK_WRITE(sc, reg_cntl0, val | MESON_PLL_CNTL_REG_EN);
1389 CLK_WRITE(sc, reg_cntl0, val & ~MESON_PLL_CNTL_REG_RST);
1401 CLK_WRITE(sc, clk->u.mux.reg, val | __BIT(11));
1442 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL0, cntl0 |
1444 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL0, cntl0 |
1447 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL1, 0);
1448 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL2,
1450 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL3, cntl3);
1451 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL4, cntl4);
1453 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL5, cntl5);
1455 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL5, cntl5 |
1457 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL4, cntl4 |
1460 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL0, cntl0 |
1464 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL0, cntl0 |
1467 CLK_WRITE(sc, HHI_PCIE_PLL_CNTL2,