Lines Matching refs:MESON_CLK_PLL_REG
187 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(28)), /* enable */ \
188 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BITS(7,0)), /* m */ \
189 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BITS(14,10)),/* n */ \
190 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL1, __BITS(16,0)), /* frac */ \
191 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(31)), /* l */ \
192 MESON_CLK_PLL_REG(HHI_FIX_PLL_CNTL0, __BIT(29)), /* reset */ \
205 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(28)), /* enable */ \
206 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BITS(7,0)), /* m */ \
207 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BITS(14,10)),/* n */ \
209 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(31)), /* l */ \
210 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL0, __BIT(29)), /* reset */ \
223 MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BIT(28)), /* enable */ \
224 MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BITS(7,0)), /* m */ \
225 MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BITS(14,10)),/* n */ \
227 MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BIT(31)), /* l */ \
228 MESON_CLK_PLL_REG(HHI_SYS1_PLL_CNTL0, __BIT(29)), /* reset */ \
305 MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BITS(13,0)), /* sdm */ \
306 MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BIT(30)), /* sdm_enable */ \
307 MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BITS(28,20)), /* n2 */ \
308 MESON_CLK_PLL_REG(HHI_MPLL_CNTL1, __BIT(29)), /* ssen */ \
313 MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BITS(13,0)), /* sdm */ \
314 MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BIT(30)), /* sdm_enable */ \
315 MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BITS(28,20)), /* n2 */ \
316 MESON_CLK_PLL_REG(HHI_MPLL_CNTL3, __BIT(29)), /* ssen */ \
321 MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BITS(13,0)), /* sdm */ \
322 MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BIT(30)), /* sdm_enable */ \
323 MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BITS(28,20)), /* n2 */ \
324 MESON_CLK_PLL_REG(HHI_MPLL_CNTL5, __BIT(29)), /* ssen */ \
903 MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BIT(28)), /* enable */ \
904 MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BITS(7,0)), /* m */ \
905 MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BITS(14,10)),/* n */ \
906 MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL1, __BITS(15,0)),/* frac */ \
907 MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BIT(30)), /* l */ \
908 MESON_CLK_PLL_REG(HHI_HDMI_PLL_CNTL0, __BIT(29)), /* reset */ \
951 MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BIT(28)), /* enable */ \
952 MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BITS(7,0)), /* m */ \
953 MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BITS(14,10)),/* n */ \
954 MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL1, __BITS(11,0)),/* frac */ \
955 MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BIT(31)), /* l */ \
956 MESON_CLK_PLL_REG(HHI_PCIE_PLL_CNTL0, __BIT(29)), /* reset */ \
Indexes created Mon Oct 20 03:09:53 GMT 2025