Cross Reference: /src/sys/arch/arm/arm32/pmap.c

Lines Matching refs:arm_cache_prefer_mask
787 	KASSERTMSG(arm_cache_prefer_mask == 0 || (((md)->pvh_attrs & PVF_WRITE) == 0) == ((md)->urw_mappings + (md)->krw_mappings == 0), \
1040 	if (arm_cache_prefer_mask != 0 && (flags & PVF_WRITE) != 0) {
1162 	if (arm_cache_prefer_mask != 0) {
1248 	if (arm_cache_prefer_mask != 0) {
2040 	if (arm_cache_prefer_mask == 0)
2074 		tst_mask &= arm_cache_prefer_mask;
2078 				if (tst_mask != (pv->pv_va & arm_cache_prefer_mask))
2092 				if (tst_mask != (pv->pv_va & arm_cache_prefer_mask)) {
2113 					KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0);
2146 				    & arm_cache_prefer_mask;
2163 		    | (va & arm_cache_prefer_mask)
2168 	} else if (((md->pvh_attrs ^ va) & arm_cache_prefer_mask) == 0) {
2197 				tst_mask = md->pvh_attrs & arm_cache_prefer_mask;
2199 					KDASSERT(((tst_mask ^ pv->pv_va) & arm_cache_prefer_mask) == 0);
2240 			KASSERT(((md->pvh_attrs ^ va) & arm_cache_prefer_mask) != 0);
2242 			md->pvh_attrs |= (va & arm_cache_prefer_mask);
2269 				md->pvh_attrs |= (va & arm_cache_prefer_mask);
2480 				if (arm_cache_prefer_mask != 0) {
2662 	KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & PVF_COLORED);
2726 	if (arm_cache_prefer_mask == 0)
2737 			end_va = arm_cache_prefer_mask;
2741 			va_offset = md->pvh_attrs & arm_cache_prefer_mask;
2753 		end_va = arm_cache_prefer_mask;
2759 		va_offset = md->pvh_attrs & arm_cache_prefer_mask;
2786 		    && va_offset == (md->pvh_attrs & arm_cache_prefer_mask))
2879 	KASSERT(arm_cache_prefer_mask == 0 || pmap_is_page_colored_p(md));
3004 	if (arm_cache_prefer_mask != 0) {
3698 	KASSERT(arm_cache_prefer_mask == 0 || md->pvh_attrs & (PVF_COLORED|PVF_NC));
3784 		if (opg && arm_cache_prefer_mask != 0) {
3842 			KASSERT(arm_cache_prefer_mask == 0 || (va & PVF_COLORED) == 0);
3846 			    && ((va ^ md->pvh_attrs) & arm_cache_prefer_mask)) {
3863 			    | (va & arm_cache_prefer_mask);
3869 		} else if (arm_cache_prefer_mask != 0) {
3944 					if (arm_cache_prefer_mask != 0) {
3950 				} else if (arm_cache_prefer_mask != 0) {
5472 	vsize_t mask = arm_cache_prefer_mask | (PAGE_SIZE - 1);
5504 	const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask;
5514 	   || va_offset == (pa & arm_cache_prefer_mask);
5551 		md->pvh_attrs &= ~arm_cache_prefer_mask;
5552 		md->pvh_attrs |= (pa & arm_cache_prefer_mask);
5636 	const vsize_t va_offset = md->pvh_attrs & arm_cache_prefer_mask;
5642 	   || va_offset == (pa & arm_cache_prefer_mask);
5741 	const vsize_t src_va_offset = src_md->pvh_attrs & arm_cache_prefer_mask;
5742 	const vsize_t dst_va_offset = dst_md->pvh_attrs & arm_cache_prefer_mask;
5753 	    || src_va_offset == (src & arm_cache_prefer_mask);
5755 	    || dst_va_offset == (dst & arm_cache_prefer_mask);
5777 	KASSERT(arm_cache_prefer_mask == 0 || src_md->pvh_attrs & (PVF_COLORED|PVF_NC));
5826 		dst_md->pvh_attrs &= ~arm_cache_prefer_mask;
5827 		dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask);
5858 		dst_md->pvh_attrs &= ~arm_cache_prefer_mask;
5859 		dst_md->pvh_attrs |= (dst & arm_cache_prefer_mask);
5961 		    arm_cache_prefer_mask,
5962 		    va & arm_cache_prefer_mask,
6511 	virtual_avail = (virtual_avail + arm_cache_prefer_mask) & ~arm_cache_prefer_mask;
6512 	nptes = (arm_cache_prefer_mask >> L2_S_SHIFT) + 1;
8298 	if (arm_cache_prefer_mask != 0) {
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