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Lines Matching defs:EMAC_READ

81 #define EMAC_READ(x) \
86 #define EMAC_READ(x) ETHREG(x)
151 	//(void)EMAC_READ(ETH_ISR);
152 	u = EMAC_READ(ETH_TSR);
156 	u = EMAC_READ(ETH_RSR);
184 	tsr = EMAC_READ(ETH_TSR);
222 	imr = ~EMAC_READ(ETH_IMR);
229 	isr = EMAC_READ(ETH_ISR) & imr;
233 	EMAC_READ(ETH_RSR);		// get receive status register
240 		ctl = EMAC_READ(ETH_CTL);		// get current control register value
313 	irq = EMAC_READ(IntStsC);
344 //	(void)EMAC_READ(ETH_ISR);
345 	u = EMAC_READ(ETH_TSR);
349 	u = EMAC_READ(ETH_RSR);
477 //	(void)EMAC_READ(ETH_ISR); // why
514 	while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE))
516 	*val = EMAC_READ(ETH_MAN) & ETH_MAN_DATA;
533 	while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE))
549 	reg = EMAC_READ(ETH_CFG);
565 	if_statadd(ifp, if_collisions, EMAC_READ(ETH_SCOL) + EMAC_READ(ETH_MCOL));
567 	misses = EMAC_READ(ETH_DRFC);
700 		device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG));
740 //	(void)EMAC_READ(ETH_ISR);
741 	u = EMAC_READ(ETH_TSR);
745 	u = EMAC_READ(ETH_RSR);
767 	uint32_t ctl = EMAC_READ(ETH_CTL);
768 	uint32_t cfg = EMAC_READ(ETH_CFG);