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Lines Matching refs:ETH_CTL

144 	EMAC_WRITE(ETH_CTL, 0);			// disable everything
232 		ctl = EMAC_READ(ETH_CTL);		// get current control register value
233 		EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);	// disable receiver
235 		EMAC_WRITE(ETH_CTL, ctl |  ETH_CTL_RE);	// re-enable receiver
330 	EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);	// disable everything
347 	EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);
472 	EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
692 		device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG));
709 	EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
726 	EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);	// disable everything
759 	uint32_t ctl = EMAC_READ(ETH_CTL);
763 	EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
863 	EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);