Cross Reference: /src/sys/arch/arm/imx/imx23

Lines Matching refs:channel
261  * Initialize DMA channel.
264 apbdma_chan_init(struct apbdma_softc *sc, unsigned int channel)
270 	DMA_WR(sc, HW_APB_CTRL1_SET, (1<<channel)<<16);
278  * Set command chain for DMA channel.
280 #define HW_APB_CHN_NXTCMDAR(base, channel)	(base + (0x70 * channel))
282 apbdma_chan_set_chain(struct apbdma_softc *sc, unsigned int channel,
288 		reg = HW_APB_CHN_NXTCMDAR(HW_APBH_CH0_NXTCMDAR, channel);
290 		reg = HW_APB_CHN_NXTCMDAR(HW_APBX_CH0_NXTCMDAR, channel);
302 #define HW_APB_CHN_SEMA(base, channel)	(base + (0x70 * channel))
304 apbdma_run(struct apbdma_softc *sc, unsigned int channel)
310 		reg = HW_APB_CHN_SEMA(HW_APBH_CH0_SEMA, channel);
313 		reg = HW_APB_CHN_SEMA(HW_APBX_CH0_SEMA, channel);
328 apbdma_ack_intr(struct apbdma_softc *sc, unsigned int channel)
333 		DMA_WR(sc, HW_APB_CTRL1_CLR, (1<<channel));
335 		DMA_WR(sc, HW_APB_CTRL1_CLR, (1<<channel));
346 apbdma_ack_error_intr(struct apbdma_softc *sc, unsigned int channel)
350 	DMA_WR(sc, HW_APB_CTRL2_CLR, (1<<channel));
360 apbdma_intr_status(struct apbdma_softc *sc, unsigned int channel)
369 	if (DMA_RD(sc, HW_APB_CTRL1) & (1<<channel))
373 	if (DMA_RD(sc, HW_APB_CTRL2) & (1<<channel)) {
374 		if (DMA_RD(sc, HW_APB_CTRL2) & (1<<channel)<<16)
386  * Reset DMA channel.
390 apbdma_chan_reset(struct apbdma_softc *sc, unsigned int channel)
397 		    __SHIFTIN((1<<channel), HW_APBH_CTRL0_RESET_CHANNEL));
401 			__SHIFTIN((1<<channel), HW_APBH_CTRL0_RESET_CHANNEL));
402 		while(DMA_RD(sc, HW_APBX_CHANNEL_CTRL) & (1<<channel));
411 apbdma_wait(struct apbdma_softc *sc, unsigned int channel)
417 		while (DMA_RD(sc, HW_APB_CHN_SEMA(HW_APBH_CH0_SEMA, channel)) & HW_APBH_CH0_SEMA_PHORE)
420 		while (DMA_RD(sc, HW_APB_CHN_SEMA(HW_APBX_CH0_SEMA, channel)) & HW_APBX_CH0_SEMA_PHORE)
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