Lines Matching refs:__BITS
51 #define HW_DIGCTL_CTRL_RSVD2 __BITS(28, 27)
64 #define HW_DIGCTL_CTRL_SAIF_CLKMUX_SEL __BITS(14, 13)
91 #define HW_DIGCTL_STATUS_RSVD2 __BITS(27, 11)
99 #define HW_DIGCTL_STATUS_PACKAGE_TYPE __BITS(3, 1)
110 #define HW_DIGCTL_HCLKCOUNT_COUNT __BITS(31, 0)
120 #define HW_DIGCTL_RAMCTRL_RSVD1 __BITS(31, 12)
121 #define HW_DIGCTL_RAMCTRL_SPEED_SELECT __BITS(11, 8)
122 #define HW_DIGCTL_RAMCTRL_RSVD0 __BITS(7, 1)
133 #define HW_DIGCTL_RAMREPAIR_RSVD1 __BITS(31, 16)
134 #define HW_DIGCTL_RAMREPAIR_ADDR __BITS(15, 0)
144 #define HW_DIGCTL_ROMCTRL_RSVD0 __BITS(31, 4)
145 #define HW_DIGCTL_ROMCTRL_RD_MARGIN __BITS(3, 0)
152 #define HW_DIGCTL_WRITEONCE_BITS __BITS(31, 0)
159 #define HW_DIGCTL_ENTROPY_VALUE __BITS(31, 0)
166 #define HW_DIGCTL_ENTROPY_VALUE __BITS(31, 0)
176 #define HW_DIGCTL_SJTAGDBG_RSVD2 __BITS(31, 27)
177 #define HW_DIGCTL_SJTAGDBG_SJTAG_STATE __BITS(26, 16)
178 #define HW_DIGCTL_SJTAGDBG_RSVD1 __BITS(15, 11)
182 #define HW_DIGCTL_SJTAGDBG_DELAYED_ACTIVE __BITS(7, 4)
196 #define HW_DIGCTL_MICROSECONDS_VALUE __BITS(31, 0)
203 #define HW_DIGCTL_DBGRD_COMPLEMENT __BITS(31, 0)
210 #define HW_DIGCTL_DBG_VALUE __BITS(31, 0)
220 #define HW_DIGCTL_OCRAM_BIST_CSR_RSVD1 __BITS(31, 11)
224 #define HW_DIGCTL_OCRAM_BIST_CSR_RSVD0 __BITS(7, 4)
238 #define HW_DIGCTL_OCRAM_STATUS0_FAILDATA00 __BITS(31, 0)
248 #define HW_DIGCTL_OCRAM_STATUS1_FAILDATA01 __BITS(31, 0)
258 #define HW_DIGCTL_OCRAM_STATUS2_FAILDATA10 __BITS(31, 0)
268 #define HW_DIGCTL_OCRAM_STATUS3_FAILDATA20 __BITS(31, 0)
278 #define HW_DIGCTL_OCRAM_STATUS4_FAILDATA20 __BITS(31, 0)
288 #define HW_DIGCTL_OCRAM_STATUS5_FAILDATA21 __BITS(31, 0)
298 #define HW_DIGCTL_OCRAM_STATUS6_FAILDATA30 __BITS(31, 0)
308 #define HW_DIGCTL_OCRAM_STATUS7_FAILDATA31 __BITS(31, 0)
318 #define HW_DIGCTL_OCRAM_STATUS8_RSVD3 __BITS(31, 29)
319 #define HW_DIGCTL_OCRAM_STATUS8_FAILADDR01 __BITS(28, 16)
320 #define HW_DIGCTL_OCRAM_STATUS8_RSVD2 __BITS(15, 13)
321 #define HW_DIGCTL_OCRAM_STATUS8_FAILADDR00 __BITS(12, 0)
331 #define HW_DIGCTL_OCRAM_STATUS9_RSVD3 __BITS(31, 29)
332 #define HW_DIGCTL_OCRAM_STATUS9_FAILADDR11 __BITS(28, 16)
333 #define HW_DIGCTL_OCRAM_STATUS9_RSVD2 __BITS(15, 13)
334 #define HW_DIGCTL_OCRAM_STATUS9_FAILADDR10 __BITS(12, 0)
344 #define HW_DIGCTL_OCRAM_STATUS10_RSVD3 __BITS(31, 29)
345 #define HW_DIGCTL_OCRAM_STATUS10_FAILADDR21 __BITS(28, 16)
346 #define HW_DIGCTL_OCRAM_STATUS10_RSVD2 __BITS(15, 13)
347 #define HW_DIGCTL_OCRAM_STATUS10_FAILADDR20 __BITS(12, 0)
357 #define HW_DIGCTL_OCRAM_STATUS11_RSVD3 __BITS(31, 29)
358 #define HW_DIGCTL_OCRAM_STATUS11_FAILADDR31 __BITS(28, 16)
359 #define HW_DIGCTL_OCRAM_STATUS11_RSVD2 __BITS(15, 13)
360 #define HW_DIGCTL_OCRAM_STATUS11_FAILADDR30 __BITS(12, 0)
370 #define HW_DIGCTL_OCRAM_STATUS12_RSVD3 __BITS(31, 28)
371 #define HW_DIGCTL_OCRAM_STATUS12_FAILSTATE11 __BITS(27, 24)
372 #define HW_DIGCTL_OCRAM_STATUS12_RSVD2 __BITS(23, 20)
373 #define HW_DIGCTL_OCRAM_STATUS12_FAILSTATE10 __BITS(19, 16)
374 #define HW_DIGCTL_OCRAM_STATUS12_RSVD1 __BITS(15, 12)
375 #define HW_DIGCTL_OCRAM_STATUS12_FAILSTATE01 __BITS(11, 8)
376 #define HW_DIGCTL_OCRAM_STATUS12_RSVD0 __BITS(7, 4)
377 #define HW_DIGCTL_OCRAM_STATUS12_FAILSTATE00 __BITS(3, 0)
387 #define HW_DIGCTL_OCRAM_STATUS13_RSVD3 __BITS(31, 28)
388 #define HW_DIGCTL_OCRAM_STATUS13_FAILSTATE31 __BITS(27, 24)
389 #define HW_DIGCTL_OCRAM_STATUS13_RSVD2 __BITS(23, 20)
390 #define HW_DIGCTL_OCRAM_STATUS13_FAILSTATE30 __BITS(19, 16)
391 #define HW_DIGCTL_OCRAM_STATUS13_RSVD1 __BITS(15, 12)
392 #define HW_DIGCTL_OCRAM_STATUS13_FAILSTATE21 __BITS(11, 8)
393 #define HW_DIGCTL_OCRAM_STATUS13_RSVD0 __BITS(7, 4)
394 #define HW_DIGCTL_OCRAM_STATUS13_FAILSTATE20 __BITS(3, 0)
401 #define HW_DIGCTL_SCRATCH0_PTR __BITS(31, 0)
408 #define HW_DIGCTL_SCRATCH1_PTR __BITS(31, 0)
415 #define HW_DIGCTL_ARMCACHE_RSVD4 __BITS(31, 18)
416 #define HW_DIGCTL_ARMCACHE_VALID_SS __BITS(17, 16)
417 #define HW_DIGCTL_ARMCACHE_RSVD3 __BITS(15, 14)
418 #define HW_DIGCTL_ARMCACHE_DRTY_SS __BITS(13, 12)
419 #define HW_DIGCTL_ARMCACHE_RSVD2 __BITS(11, 10)
420 #define HW_DIGCTL_ARMCACHE_CACHE_SS __BITS(9, 8)
421 #define HW_DIGCTL_ARMCACHE_RSVD1 __BITS(7, 6)
422 #define HW_DIGCTL_ARMCACHE_DTAG_SS __BITS(5, 4)
423 #define HW_DIGCTL_ARMCACHE_RSVD0 __BITS(3, 2)
424 #define HW_DIGCTL_ARMCACHE_ITAG_SS __BITS(1, 0)
431 #define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR __BITS(31, 0)
438 #define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR __BITS(31, 0)
445 #define HW_DIGCTL_SGTL_COPYRIGHT __BITS(31, 0)
452 #define HW_DIGCTL_CHIPID_PRODUCT_CODE __BITS(31, 16)
453 #define HW_DIGCTL_CHIPID_RSVD0 __BITS(16, 8)
454 #define HW_DIGCTL_CHIPID_REVISION __BITS(7, 0)
461 #define HW_DIGCTL_AHB_STATS_SELECT_RSVD3 __BITS(31, 28)
462 #define HW_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT __BITS(27, 24)
463 #define HW_DIGCTL_AHB_STATS_SELECT_RSVD2 __BITS(23, 20)
464 #define HW_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT __BITS(19, 16)
465 #define HW_DIGCTL_AHB_STATS_SELECT_RSVD1 __BITS(15, 12)
466 #define HW_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT __BITS(11, 8)
467 #define HW_DIGCTL_AHB_STATS_SELECT_RSVD0 __BITS(7, 4)
468 #define HW_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT __BITS(3, 0)
475 #define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT __BITS(31, 0)
482 #define HW_DIGCTL_L0_AHB_DATA_STALLED_COUNT __BITS(31, 0)
489 #define HW_DIGCTL_L0_AHB_DATA_CYCLES_COUNT __BITS(31, 0)
496 #define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT __BITS(31, 0)
503 #define HW_DIGCTL_L1_AHB_DATA_STALLED_COUNT __BITS(31, 0)
510 #define HW_DIGCTL_L1_AHB_DATA_STALLED_COUNT __BITS(31, 0)
517 #define HW_DIGCTL_L1_AHB_DATA_CYCLES_COUNT __BITS(31, 0)
524 #define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT __BITS(31, 0)
531 #define HW_DIGCTL_L2_AHB_DATA_STALLED_COUNT __BITS(31, 0)
538 #define HW_DIGCTL_L2_AHB_DATA_CYCLES_COUNT __BITS(31, 0)
545 #define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT __BITS(31, 0)
552 #define HW_DIGCTL_L3_AHB_DATA_STALLED_COUNT __BITS(31, 0)
559 #define HW_DIGCTL_L3_AHB_DATA_CYCLES_COUNT __BITS(31, 0)
566 #define HW_DIGCTL_EMICLK_DELAY_RSVD0 __BITS(31, 5)
567 #define HW_DIGCTL_EMICLK_DELAY_NUM_TAPS __BITS(4, 0)
Indexes created Mon Oct 20 11:09:49 GMT 2025