Lines Matching refs:__BITS
52 #define HW_EMI_CTRL_AXI_DEPTH __BITS(27, 26)
55 #define HW_EMI_CTRL_ARB_MODE __BITS(23, 22)
57 #define HW_EMI_CTRL_PORT_PRIORITY_ORDER __BITS(20, 16)
59 #define HW_EMI_CTRL_PRIORITY_WRITE_ITER __BITS(14, 12)
61 #define HW_EMI_CTRL_HIGH_PRIORITY_WRITE __BITS(10, 8)
66 #define HW_EMI_CTRL_RSVD0 __BITS(3, 0)
73 #define HW_EMI_VERSION_MAJOR __BITS(31, 24)
74 #define HW_EMI_VERSION_MINOR __BITS(23, 16)
75 #define HW_EMI_VERSION_STEP __BITS(15, 0)
82 #define HW_DRAM_CTL00_RSVD4 __BITS(31, 25)
84 #define HW_DRAM_CTL00_RSVD3 __BITS(23, 17)
86 #define HW_DRAM_CTL00_RSVD2 __BITS(15, 9)
88 #define HW_DRAM_CTL00_RSVD1 __BITS(7, 1)
96 #define HW_DRAM_CTL01_RSVD4 __BITS(31, 25)
98 #define HW_DRAM_CTL01_RSVD3 __BITS(23, 17)
100 #define HW_DRAM_CTL01_RSVD2 __BITS(15, 9)
102 #define HW_DRAM_CTL01_RSVD1 __BITS(7, 1)
110 #define HW_DRAM_CTL02_RSVD4 __BITS(31, 25)
112 #define HW_DRAM_CTL02_RSVD3 __BITS(23, 17)
116 #define HW_DRAM_CTL02_RSVD1 __BITS(7, 1)
124 #define HW_DRAM_CTL03_RSVD4 __BITS(31, 25)
126 #define HW_DRAM_CTL03_RSVD3 __BITS(23, 17)
128 #define HW_DRAM_CTL03_RSVD2 __BITS(15, 9)
130 #define HW_DRAM_CTL03_RSVD1 __BITS(7, 1)
138 #define HW_DRAM_CTL04_RSVD4 __BITS(31, 25)
140 #define HW_DRAM_CTL04_RSVD3 __BITS(23, 17)
142 #define HW_DRAM_CTL04_RSVD2 __BITS(15, 9)
144 #define HW_DRAM_CTL04_RSVD1 __BITS(7, 1)
152 #define HW_DRAM_CTL05_RSVD4 __BITS(31, 25)
154 #define HW_DRAM_CTL05_RSVD3 __BITS(23, 17)
156 #define HW_DRAM_CTL05_RSVD2 __BITS(15, 9)
158 #define HW_DRAM_CTL05_RSVD1 __BITS(7, 1)
166 #define HW_DRAM_CTL06_RSVD4 __BITS(31, 25)
168 #define HW_DRAM_CTL06_RSVD3 __BITS(23, 17)
170 #define HW_DRAM_CTL06_RSVD2 __BITS(15, 9)
172 #define HW_DRAM_CTL06_RSVD1 __BITS(7, 1)
180 #define HW_DRAM_CTL07_RSVD4 __BITS(31, 25)
182 #define HW_DRAM_CTL07_RSVD3 __BITS(23, 17)
184 #define HW_DRAM_CTL07_RSVD2 __BITS(15, 9)
186 #define HW_DRAM_CTL07_RSVD1 __BITS(7, 1)
194 #define HW_DRAM_CTL08_RSVD4 __BITS(31, 25)
196 #define HW_DRAM_CTL08_RSVD3 __BITS(23, 17)
198 #define HW_DRAM_CTL08_RSVD2 __BITS(15, 9)
200 #define HW_DRAM_CTL08_RSVD1 __BITS(7, 1)
208 #define HW_DRAM_CTL09_RSVD4 __BITS(31, 26)
209 #define HW_DRAM_CTL09_OUT_OF_RANGE_TYPE __BITS(25, 24)
210 #define HW_DRAM_CTL09_RSVD3 __BITS(23, 18)
211 #define HW_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID __BITS(17, 16)
212 #define HW_DRAM_CTL09_RSVD2 __BITS(15, 9)
214 #define HW_DRAM_CTL09_RSVD1 __BITS(7, 1)
222 #define HW_DRAM_CTL10_RSVD4 __BITS(31, 27)
223 #define HW_DRAM_CTL10_AGE_COUNT __BITS(26, 24)
224 #define HW_DRAM_CTL10_RSVD3 __BITS(23, 19)
225 #define HW_DRAM_CTL10_ADDR_PINS __BITS(18, 16)
226 #define HW_DRAM_CTL10_RSVD2 __BITS(15, 10)
227 #define HW_DRAM_CTL10_TEMRS __BITS(9, 8)
228 #define HW_DRAM_CTL10_RSVD1 __BITS(7, 2)
229 #define HW_DRAM_CTL10_Q_FULLNESS __BITS(1, 0)
236 #define HW_DRAM_CTL11_RSVD4 __BITS(31, 27)
237 #define HW_DRAM_CTL11_MAX_CS_REG __BITS(26, 24)
238 #define HW_DRAM_CTL11_RSVD3 __BITS(23, 19)
239 #define HW_DRAM_CTL11_COMMAND_AGE_COUNT __BITS(18, 16)
240 #define HW_DRAM_CTL11_RSVD2 __BITS(15, 11)
241 #define HW_DRAM_CTL11_COLUMN_SIZE __BITS(10, 8)
242 #define HW_DRAM_CTL11_RSVD1 __BITS(7, 3)
243 #define HW_DRAM_CTL11_CASLAT __BITS(2, 0)
250 #define HW_DRAM_CTL12_RSVD3 __BITS(31, 27)
251 #define HW_DRAM_CTL12_TWR_INT __BITS(26, 24)
252 #define HW_DRAM_CTL12_RSVD2 __BITS(23, 19)
253 #define HW_DRAM_CTL12_TRRD __BITS(18 ,16)
254 #define HW_DRAM_CTL12_OBSOLETE __BITS(15, 8)
255 #define HW_DRAM_CTL12_RSVD1 __BITS(7, 3)
256 #define HW_DRAM_CTL12_TCKE __BITS(2, 0)
263 #define HW_DRAM_CTL13_RSVD4 __BITS(31, 28)
264 #define HW_DRAM_CTL13_CASLAT_LIN_GATE __BITS(27, 24)
265 #define HW_DRAM_CTL13_RSVD3 __BITS(23, 20)
266 #define HW_DRAM_CTL13_CASLAT_LIN __BITS(19, 16)
267 #define HW_DRAM_CTL13_RSVD2 __BITS(15, 12)
268 #define HW_DRAM_CTL13_APREBIT __BITS(11, 8)
269 #define HW_DRAM_CTL13_RSVD1 __BITS(7, 3)
270 #define HW_DRAM_CTL13_TWTR __BITS(2, 0)
277 #define HW_DRAM_CTL14_RSVD4 __BITS(31, 28)
278 #define HW_DRAM_CTL14_MAX_COL_REG __BITS(27, 24)
279 #define HW_DRAM_CTL14_RSVD3 __BITS(23, 20)
280 #define HW_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE __BITS(19, 16)
281 #define HW_DRAM_CTL14_RSVD2 __BITS(15, 12)
282 #define HW_DRAM_CTL14_INITAREF __BITS(11, 8)
283 #define HW_DRAM_CTL14_RSVD1 __BITS(7, 4)
284 #define HW_DRAM_CTL14_CS_MAP __BITS(3, 0)
291 #define HW_DRAM_CTL15_RSVD4 __BITS(31, 28)
292 #define HW_DRAM_CTL15_TRP __BITS(27, 24)
293 #define HW_DRAM_CTL15_RSVD3 __BITS(23, 20)
294 #define HW_DRAM_CTL15_TDAL __BITS(19, 16)
295 #define HW_DRAM_CTL15_RSVD2 __BITS(15, 12)
296 #define HW_DRAM_CTL15_PORT_BUSY __BITS(11, 8)
297 #define HW_DRAM_CTL15_RSVD1 __BITS(7, 4)
298 #define HW_DRAM_CTL15_MAX_ROW_REG __BITS(3, 0)
305 #define HW_DRAM_CTL16_RSVD4 __BITS(31, 29)
306 #define HW_DRAM_CTL16_TMRD __BITS(28, 24)
307 #define HW_DRAM_CTL16_RSVD3 __BITS(23, 21)
308 #define HW_DRAM_CTL16_LOWPOWER_CONTROL __BITS(20, 16)
309 #define HW_DRAM_CTL16_RSVD2 __BITS(15, 13)
310 #define HW_DRAM_CTL16_LOWPOWER_AUTO_ENABLE __BITS(12, 8)
311 #define HW_DRAM_CTL16_RSVD1 __BITS(7, 4)
312 #define HW_DRAM_CTL16_INT_ACK __BITS(3, 0)
319 #define HW_DRAM_CTL17_DLL_START_POINT __BITS(31, 24)
320 #define HW_DRAM_CTL17_DLL_LOCK __BITS(23, 16)
321 #define HW_DRAM_CTL17_DLL_INCREMENT __BITS(15, 8)
322 #define HW_DRAM_CTL17_RSVD1 __BITS(7, 5)
323 #define HW_DRAM_CTL17_TRC __BITS(4, 0)
331 #define HW_DRAM_CTL18_DLL_DQS_DELAY_1 __BITS(30, 24)
333 #define HW_DRAM_CTL18_DLL_DQS_DELAY_0 __BITS(22, 16)
334 #define HW_DRAM_CTL18_RSVD2 __BITS(15, 13)
335 #define HW_DRAM_CTL18_INT_STATUS __BITS(12, 8)
336 #define HW_DRAM_CTL18_RSVD1 __BITS(7, 5)
337 #define HW_DRAM_CTL18_INT_MASK __BITS(4, 0)
344 #define HW_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS __BITS(31, 24)
346 #define HW_DRAM_CTL19_DQS_OUT_SHIFT __BITS(22, 16)
347 #define HW_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 __BITS(15, 8)
348 #define HW_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 __BITS(7, 0)
355 #define HW_DRAM_CTL20_TRCD_INT __BITS(31, 24)
356 #define HW_DRAM_CTL20_TRAS_MIN __BITS(23, 16)
357 #define HW_DRAM_CTL20_WR_DQS_SHIFT_BYPASS __BITS(15, 8)
359 #define HW_DRAM_CTL20_WR_DQS_SHIFT __BITS(6, 0)
366 #define HW_DRAM_CTL21_OBSOLETE __BITS(31, 24)
367 #define HW_DRAM_CTL21_RSVD1 __BITS(23, 18)
368 #define HW_DRAM_CTL21_OUT_OF_RANGE_LENGTH __BITS(17, 8)
369 #define HW_DRAM_CTL21_TRFC __BITS(7, 0)
376 #define HW_DRAM_CTL22_RSVD2 __BITS(31, 27)
377 #define HW_DRAM_CTL22_AHB0_WRCNT __BITS(26, 16)
378 #define HW_DRAM_CTL22_RSVD1 __BITS(15, 11)
379 #define HW_DRAM_CTL22_AHB0_RDCNT __BITS(10, 0)
386 #define HW_DRAM_CTL23_RSVD2 __BITS(31, 27)
387 #define HW_DRAM_CTL23_AHB1_WRCNT __BITS(26, 16)
388 #define HW_DRAM_CTL23_RSVD1 __BITS(15, 11)
389 #define HW_DRAM_CTL23_AHB1_RDCNT __BITS(10, 0)
396 #define HW_DRAM_CTL24_RSVD2 __BITS(31, 27)
397 #define HW_DRAM_CTL24_AHB2_WRCNT __BITS(26, 16)
398 #define HW_DRAM_CTL24_RSVD1 __BITS(15, 11)
399 #define HW_DRAM_CTL24_AHB2_RDCNT __BITS(10, 0)
406 #define HW_DRAM_CTL25_RSVD2 __BITS(31, 27)
407 #define HW_DRAM_CTL25_AHB3_WRCNT __BITS(26, 16)
408 #define HW_DRAM_CTL25_RSVD1 __BITS(15, 11)
409 #define HW_DRAM_CTL25_AHB3_RDCNT __BITS(10, 0)
416 #define HW_DRAM_CTL26_OBSOLETE __BITS(31, 16)
417 #define HW_DRAM_CTL26_RSVD1 __BITS(15, 12)
418 #define HW_DRAM_CTL26_TREF __BITS(11, 0)
425 #define HW_DRAM_CTL27_OBSOLETE __BITS(31, 0)
432 #define HW_DRAM_CTL28_OBSOLETE __BITS(31, 0)
439 #define HW_DRAM_CTL29_LOWPOWER_INTERNAL_CNT __BITS(31, 16)
440 #define HW_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT __BITS(15, 0)
447 #define HW_DRAM_CTL30_LOWPOWER_REFRESH_HOLD __BITS(31, 16)
448 #define HW_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT __BITS(15, 0)
455 #define HW_DRAM_CTL31_TDLL __BITS(31, 16)
456 #define HW_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT __BITS(15, 0)
463 #define HW_DRAM_CTL32_TXSNR __BITS(31, 16)
464 #define HW_DRAM_CTL32_TRAS_MAX __BITS(15, 0)
471 #define HW_DRAM_CTL33_VERSION __BITS(31, 16)
472 #define HW_DRAM_CTL33_TXSR __BITS(15, 0)
479 #define HW_DRAM_CTL34_RSVD1 __BITS(31, 24)
480 #define HW_DRAM_CTL34_TINIT __BITS(23, 0)
488 #define HW_DRAM_CTL35_OUT_OF_RANGE_ADDR __BITS(30, 0)
495 #define HW_DRAM_CTL36_RSVD5 __BITS(31, 25)
497 #define HW_DRAM_CTL36_RSVD4 __BITS(23, 17)
499 #define HW_DRAM_CTL36_RSVD3 __BITS(15, 9)
501 #define HW_DRAM_CTL36_RSVD1 __BITS(7, 1)
509 #define HW_DRAM_CTL37_OBSOLETE __BITS(31, 24)
510 #define HW_DRAM_CTL37_RSVD2 __BITS(23, 18)
511 #define HW_DRAM_CTL37_BUS_SHARE_TIMEOUT __BITS(17, 8)
512 #define HW_DRAM_CTL37_RSVD1 __BITS(7, 1)
520 #define HW_DRAM_CTL38_RSVD2 __BITS(31, 29)
521 #define HW_DRAM_CTL38_EMRS2_DATA_0 __BITS(28, 16)
522 #define HW_DRAM_CTL38_RSVD1 __BITS(15, 13)
523 #define HW_DRAM_CTL38_EMRS1_DATA __BITS(12, 0)
530 #define HW_DRAM_CTL39_RSVD2 __BITS(31, 29)
531 #define HW_DRAM_CTL39_EMRS2_DATA_2 __BITS(28, 16)
532 #define HW_DRAM_CTL39_RSVD1 __BITS(15, 13)
533 #define HW_DRAM_CTL39_EMRS2_DATA_1 __BITS(12, 0)
540 #define HW_DRAM_CTL40_TPDEX __BITS(31, 16)
541 #define HW_DRAM_CTL40_RSVD1 __BITS(15, 13)
542 #define HW_DRAM_CTL40_EMRS2_DATA_3 __BITS(12, 0)
Indexes created Fri Oct 17 23:09:53 GMT 2025