Lines Matching refs:__BIT
51 #define HW_SSP_CTRL0_SFTRST __BIT(31)
52 #define HW_SSP_CTRL0_CLKGATE __BIT(30)
53 #define HW_SSP_CTRL0_RUN __BIT(29)
54 #define HW_SSP_CTRL0_SDIO_IRQ_CHECK __BIT(28)
55 #define HW_SSP_CTRL0_LOCK_CS __BIT(27)
56 #define HW_SSP_CTRL0_IGNORE_CRC __BIT(26)
57 #define HW_SSP_CTRL0_READ __BIT(25)
58 #define HW_SSP_CTRL0_DATA_XFER __BIT(24)
60 #define HW_SSP_CTRL0_WAIT_FOR_IRQ __BIT(21)
61 #define HW_SSP_CTRL0_WAIT_FOR_CMD __BIT(20)
62 #define HW_SSP_CTRL0_LONG_RESP __BIT(19)
63 #define HW_SSP_CTRL0_CHECK_RESP __BIT(18)
64 #define HW_SSP_CTRL0_GET_RESP __BIT(17)
65 #define HW_SSP_CTRL0_ENABLE __BIT(16)
77 #define HW_SSP_CMD0_SLOW_CLKING_EN __BIT(22)
78 #define HW_SSP_CMD0_CONT_CLKING_EN __BIT(21)
79 #define HW_SSP_CMD0_APPEND_8CYC __BIT(20)
122 #define HW_SSP_CTRL1_SDIO_IRQ __BIT(31)
123 #define HW_SSP_CTRL1_SDIO_IRQ_EN __BIT(30)
124 #define HW_SSP_CTRL1_RESP_ERR_IRQ __BIT(29)
125 #define HW_SSP_CTRL1_RESP_ERR_IRQ_EN __BIT(28)
126 #define HW_SSP_CTRL1_RESP_TIMEOUT_IRQ __BIT(27)
127 #define HW_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN __BIT(26)
128 #define HW_SSP_CTRL1_DATA_TIMEOUT_IRQ __BIT(25)
129 #define HW_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN __BIT(24)
130 #define HW_SSP_CTRL1_DATA_CRC_IRQ __BIT(23)
131 #define HW_SSP_CTRL1_DATA_CRC_IRQ_EN __BIT(22)
132 #define HW_SSP_CTRL1_FIFO_UNDERRUN_IRQ __BIT(21)
133 #define HW_SSP_CTRL1_FIFO_UNDERRUN_EN __BIT(20)
134 #define HW_SSP_CTRL1_RSVD3 __BIT(19)
135 #define HW_SSP_CTRL1_RSVD2 __BIT(18)
136 #define HW_SSP_CTRL1_RECV_TIMEOUT_IRQ __BIT(17)
137 #define HW_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN __BIT(16)
138 #define HW_SSP_CTRL1_FIFO_OVERRUN_IRQ __BIT(15)
139 #define HW_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN __BIT(14)
140 #define HW_SSP_CTRL1_DMA_ENABLE __BIT(13)
141 #define HW_SSP_CTRL1_RSVD1 __BIT(12)
142 #define HW_SSP_CTRL1_SLAVE_OUT_DISABLE __BIT(11)
143 #define HW_SSP_CTRL1_PHASE __BIT(10)
144 #define HW_SSP_CTRL1_POLARITY __BIT(9)
145 #define HW_SSP_CTRL1_SLAVE_MODE __BIT(8)
189 #define HW_SSP_STATUS_PRESENT __BIT(31)
190 #define HW_SSP_STATUS_RSVD5 __BIT(30)
191 #define HW_SSP_STATUS_SD_PRESENT __BIT(29)
192 #define HW_SSP_STATUS_CARD_DETECT __BIT(28)
194 #define HW_SSP_STATUS_DMASENSE __BIT(21)
195 #define HW_SSP_STATUS_DMATERM __BIT(20)
196 #define HW_SSP_STATUS_DMAREQ __BIT(19)
197 #define HW_SSP_STATUS_DMAEND __BIT(18)
198 #define HW_SSP_STATUS_SDIO_IRQ __BIT(17)
199 #define HW_SSP_STATUS_RESP_CRC_ERR __BIT(16)
200 #define HW_SSP_STATUS_RESP_ERR __BIT(15)
201 #define HW_SSP_STATUS_RESP_TIMEOUT __BIT(14)
202 #define HW_SSP_STATUS_DATA_CRC_ERR __BIT(13)
203 #define HW_SSP_STATUS_TIMEOUT __BIT(12)
204 #define HW_SSP_STATUS_RECV_TIMEOUT_STAT __BIT(11)
205 #define HW_SSP_STATUS_RSVD3 __BIT(10)
206 #define HW_SSP_STATUS_FIFO_OVRFLW __BIT(9)
207 #define HW_SSP_STATUS_FIFO_FULL __BIT(8)
208 #define HW_SSP_STATUS_RSVD2 __BIT(7, 6)
209 #define HW_SSP_STATUS_FIFO_EMPTY __BIT(5)
210 #define HW_SSP_STATUS_FIFO_UNDRFLW __BIT(4)
211 #define HW_SSP_STATUS_CMD_BUSY __BIT(3)
212 #define HW_SSP_STATUS_DATA_BUSY __BIT(2)
213 #define HW_SSP_STATUS_RSVD1 __BIT(1)
214 #define HW_SSP_STATUS_BUSY __BIT(0)
222 #define HW_SSP_DEBUG_DATA_STALL __BIT(27)
225 #define HW_SSP_DEBUG_CMD_OE __BIT(19)
229 #define HW_SSP_DEBUG_SSP_CMD __BIT(9)
230 #define HW_SSP_DEBUG_SSP_RESP __BIT(8)
Indexes created Tue Oct 21 08:09:48 GMT 2025