Lines Matching refs:x4000
129 #define ESDHC_SIZE 0x4000
150 #define SPDIF_SIZE 0x4000
153 #define PATA_UDMA_SIZE 0x4000
155 #define PATA_PIO_SIZE 0x4000
158 #define SLM_SIZE 0x4000
162 #define I2C3_SIZE 0x4000
165 #define HSI2C_SIZE 0x4000
169 #define SPBA_SIZE 0x4000
241 #define USBOH3_SIZE 0x4000
247 0x03f84000 + 0x4000 * ((n) - 1) : \
248 0x03fdc000 + 0x4000 * ((n) - 5)))
268 #define WDOG_SIZE 0x4000
271 #define GPT_SIZE 0x4000
274 #define SRTC_SIZE 0x4000
278 #define IOMUXC_SIZE 0x4000
338 #define PWM_SIZE 0x4000
341 #define SRC_SIZE 0x4000
344 #define CCM_SIZE 0x4000
347 #define GPC_SIZE 0x4000
350 #define AHBMAX_SIZE 0x4000
353 #define IIM_SIZE 0x4000
356 #define CSU_SIZE 0x4000
359 #define OWIRE_SIZE 0x4000
362 #define FIRI_SIZE 0x4000
366 #define SDMA_SIZE 0x4000
370 #define SCC_SIZE 0x4000
373 #define ROMCP_SIZE 0x4000
376 #define RTIC_SIZE 0x4000
379 #define CSPI_SIZE 0x4000
383 #define I2C_SIZE 0x4000
386 #define AUDMUX_SIZE 0x4000
406 #define EMI_SIZE 0x4000
409 #define SIM_SIZE 0x4000
412 #define FEC_SIZE 0x4000
414 #define TVE_SIZE 0x4000
416 #define VPU_SIZE 0x4000
418 #define SAHARA_SIZE 0x4000
420 #define DPLL_BASE(n) ((AIPSTZ2_BASE + 0x03F80000 + (0x4000 * ((n)-1))))
421 #define DPLL_SIZE 0x4000
Indexes created Fri Oct 31 11:10:07 GMT 2025