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Lines Matching refs:dp

66 dma_go(struct dma_ctrl *dp)
72 	if (dp->dc_flags & DMA_FL_READY) {
73 		dp->dc_flags = DMA_FL_ACTIVE;
74 		enable_irq(IRQ_DMACH0 + dp->dc_channel);
80 dma_reset(struct dma_ctrl *dp)
85 	dma_dumpdc(dp);
87 	*dp->dc_cr = DMA_CR_CLEAR;
88 	dp->dc_flags = 0;
89 	disable_irq(IRQ_DMACH0 + dp->dc_channel);
97 dma_setup(struct dma_ctrl *dp, u_char *start, int len, int readp)
104 	if (((u_int)start & (dp->dc_dmasize - 1)) ||
105 	   (len & (dp->dc_dmasize - 1))) {
109 	*dp->dc_cr = DMA_CR_CLEAR | DMA_CR_ENABLE | (readp?DMA_CR_DIR:0) |
110 	    dp->dc_dmasize;
111 	*dp->dc_cr = DMA_CR_ENABLE | (readp?DMA_CR_DIR:0) | dp->dc_dmasize;
113 	dp->dc_nextaddr = start;
114 	dp->dc_len = len;
116 	dp->dc_flags = DMA_FL_READY;
124 dma_isactive(struct dma_ctrl *dp)
127 	return dp->dc_flags & DMA_FL_ACTIVE;
134 dma_isintr(struct dma_ctrl *dp)
138 /*	printf("dma_isintr() returning %d\n", *dp->dc_st & DMA_ST_INT);*/
140 	return *dp->dc_st & DMA_ST_INT;
146 	struct dma_ctrl *dp = cookie;
147 	u_char status = (*dp->dc_st) & DMA_ST_MASK;
156 	if (!(dp->dc_flags & DMA_FL_ACTIVE)) {
159 		dma_reset(dp);
195 		printf("DMA ch %d bad status [%x]\n", dp->dc_channel, status);
196 		dma_dumpdc(dp);
208 	if (dp->dc_len == 0) goto done;
209 	PHYS(dp->dc_nextaddr, &cur);
211 	if (len > dp->dc_len) {
213 		len = dp->dc_len;
217 	dma_dumpdc(dp);
218 /*	ptsc_dump_mem(dp->dc_nextaddr, len);*/
223 	cpu_dcache_wbinv_range((vaddr_t)dp->dc_nextaddr, len);
225 	dp->dc_nextaddr += len;
226 	dp->dc_len -= len;
229 		*dp->dc_cura = (u_int)cur;
230 		*dp->dc_enda = ((u_int)cur + len - dp->dc_dmasize) |
231 				(dp->dc_len == 0 ? DMA_END_STOP : 0);
232 		if (dp->dc_len == 0) {
234 			*dp->dc_endb = (u_int)cur;
237 		*dp->dc_curb = (u_int)cur;
238 		*dp->dc_endb = ((u_int)cur + len - dp->dc_dmasize) |
239 				(dp->dc_len == 0 ? DMA_END_STOP : 0);
240 		if (dp->dc_len == 0) {
242 			*dp->dc_enda = (u_int)cur;
246 	dma_dumpdc(dp);
247 /*	ptsc_dump_mem(dp->dc_nextaddr - len, len);*/
255 	dp->dc_flags = 0;
256 	*dp->dc_cr = 0;
257 	disable_irq(IRQ_DMACH0 + dp->dc_channel);
290 	struct dma_ctrl *dp = &ctrl[ch];
296 	dp->dc_channel = ch;
297 	dp->dc_flags = 0;
298 	dp->dc_dmasize = dmasize;
299 	dp->dc_cura = (volatile u_int *)(IOMD_ADDRESS(IOMD_IO0CURA) + offset);
300 	dp->dc_enda = (volatile u_int *)(IOMD_ADDRESS(IOMD_IO0ENDA) + offset);
301 	dp->dc_curb = (volatile u_int *)(IOMD_ADDRESS(IOMD_IO0CURB) + offset);
302 	dp->dc_endb = (volatile u_int *)(IOMD_ADDRESS(IOMD_IO0ENDB) + offset);
303 	dp->dc_cr = (volatile u_char *)(IOMD_ADDRESS(IOMD_IO0CR) + offset);
304 	dp->dc_st = (volatile u_char *)(IOMD_ADDRESS(IOMD_IO0ST) + offset);
311 	dp->dc_ih.ih_func = dma_intr;
312 	dp->dc_ih.ih_arg = dp;
313 	dp->dc_ih.ih_level = ipl;
314 	dp->dc_ih.ih_name = "dma";
315 	dp->dc_ih.ih_maskaddr = (u_int) IOMD_ADDRESS(IOMD_DMARQ);
316 	dp->dc_ih.ih_maskbits = (1 << ch);
318 	if (irq_claim(IRQ_DMACH0 + ch, &dp->dc_ih))
321 	return dp;