Cross Reference: /src/sys/arch/arm/ixp12x0/ixp12x0

Lines Matching refs:irq
120 ixp12x0_enable_irq(int irq)
122 	if (irq < SYS_NIRQ) {
123 		intr_enabled |= (1U << irq);
124 		switch (irq) {
133 			panic("enable_irq:bad IRQ %d", irq);
136 		pci_intr_enabled |= (1U << (irq - SYS_NIRQ));
137 		IXPREG(IXPPCI_IRQ_ENABLE_SET) = (1U << (irq - SYS_NIRQ));
142 ixp12x0_disable_irq(int irq)
144 	if (irq < SYS_NIRQ) {
145 		intr_enabled ^= ~(1U << irq);
146 		switch (irq) {
159 		pci_intr_enabled &= ~(1U << (irq - SYS_NIRQ));
160 		IXPREG(IXPPCI_IRQ_ENABLE_CLEAR) = (1U << (irq - SYS_NIRQ));
172 	int irq, ipl;
174 	/* First, figure out which IPLs each IRQ has. */
175 	for (irq = 0; irq < NIRQ; irq++) {
177 		iq = &intrq[irq];
178 		ixp12x0_disable_irq(irq);
189 		for (irq = 0; irq < SYS_NIRQ; irq++) {
190 			if (intrq[irq].iq_levels & (1U << ipl))
191 				irqs |= (1U << irq);
194 		for (irq = 0; irq < SYS_NIRQ; irq++) {
195 			if (intrq[irq + SYS_NIRQ].iq_levels & (1U << ipl))
196 				pci_irqs |= (1U << irq);
229 	 * given IRQ.
231 	for (irq = 0; irq < NIRQ; irq++) {
235 		if (irq < SYS_NIRQ) {
236 			irqs = (1U << irq);
240 			pci_irqs = (1U << (irq - SYS_NIRQ));
242 		iq = &intrq[irq];
244 			ixp12x0_enable_irq(irq);
331 ixp12x0_intr_establish(int irq, int ipl, int (*ih_func)(void *), void *arg)
337 	printf("ixp12x0_intr_establish(irq=%d, ipl=%d, ih_func=%08x, arg=%08x)\n",
338 	       irq, ipl, (uint32_t) ih_func, (uint32_t) arg);
340 	if (irq < 0 || irq > NIRQ)
341 		panic("ixp12x0_intr_establish: IRQ %d out of range", ipl);
348 	ih->ih_irq = irq;
351 	iq = &intrq[irq];
385 	int			irq;
399 		irq = ffs(hwpend) - 1;
400 		ibit = (1U << irq);
402 		iq = &intrq[irq];
414 		irq = ffs(pci_hwpend) - 1;
415 		ibit = (1U << irq);
417 		iq = &intrq[irq + SYS_NIRQ];
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