Lines Matching refs:MVSOC_UNITID_DDR
143 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR },
145 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR },
147 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR },
149 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR },
152 MARVELL_ATTR_AXI_DDR, MVSOC_UNITID_DDR },
154 MARVELL_ATTR_AXI_DDR, MVSOC_UNITID_DDR },
157 MARVELL_ATTR_SDRAM_CS0, MVSOC_UNITID_DDR },
159 MARVELL_ATTR_SDRAM_CS1, MVSOC_UNITID_DDR },
161 MARVELL_ATTR_SDRAM_CS2, MVSOC_UNITID_DDR },
163 MARVELL_ATTR_SDRAM_CS3, MVSOC_UNITID_DDR },
1270 if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) {