Lines Matching refs:__BIT
35 #define CAR_RST_SOURCE_WDT_EN __BIT(5)
36 #define CAR_RST_SOURCE_WDT_SEL __BIT(4)
37 #define CAR_RST_SOURCE_WDT_SYS_RST_EN __BIT(2)
38 #define CAR_RST_SOURCE_WDT_COP_RST_EN __BIT(1)
39 #define CAR_RST_SOURCE_WDT_CPU_RST_EN __BIT(0)
49 #define CAR_PLLE_SS_CNTL_SSCINVERT __BIT(15)
50 #define CAR_PLLE_SS_CNTL_SSCCENTER __BIT(14)
51 #define CAR_PLLE_SS_CNTL_SSCPDMBYP __BIT(13)
52 #define CAR_PLLE_SS_CNTL_SSCBYP __BIT(12)
53 #define CAR_PLLE_SS_CNTL_INTERP_RESET __BIT(11)
54 #define CAR_PLLE_SS_CNTL_BYPASS_SS __BIT(10)
58 #define CAR_PLLP_BASE_BYPASS __BIT(31)
59 #define CAR_PLLP_BASE_ENABLE __BIT(30)
60 #define CAR_PLLP_BASE_REF_DIS __BIT(29)
61 #define CAR_PLLP_BASE_OVERRIDE __BIT(28)
62 #define CAR_PLLP_BASE_LOCK __BIT(27)
69 #define CAR_PLLP_OUTA_OUT1_OVRRIDE __BIT(2)
70 #define CAR_PLLP_OUTA_OUT1_CLKEN __BIT(1)
71 #define CAR_PLLP_OUTA_OUT1_RSTN __BIT(0)
74 #define CAR_PLLP_OUTB_OUT4_OVRRIDE __BIT(18)
75 #define CAR_PLLP_OUTB_OUT4_CLKEN __BIT(17)
76 #define CAR_PLLP_OUTB_OUT4_RSTN __BIT(16)
78 #define CAR_PLLP_OUTB_OUT3_OVRRIDE __BIT(2)
79 #define CAR_PLLP_OUTB_OUT3_CLKEN __BIT(1)
80 #define CAR_PLLP_OUTB_OUT3_RSTN __BIT(0)
83 #define CAR_PLLP_OUTC_OUT5_OVERRIDE __BIT(18)
84 #define CAR_PLLP_OUTC_OUT5_CLKEN __BIT(17)
85 #define CAR_PLLP_OUTC_OUT5_RSTN __BIT(16)
89 #define CAR_PLLC_BASE_BYPASS __BIT(31)
90 #define CAR_PLLC_BASE_ENABLE __BIT(30)
91 #define CAR_PLLC_BASE_REF_DIS __BIT(29)
92 #define CAR_PLLC_BASE_LOCK_OVERRIDE __BIT(27)
93 #define CAR_PLLC_BASE_LOCK __BIT(26)
99 #define CAR_PLLU_BASE_BYPASS __BIT(31)
100 #define CAR_PLLU_BASE_ENABLE __BIT(30)
101 #define CAR_PLLU_BASE_REF_DIS __BIT(29)
102 #define CAR_PLLU_BASE_LOCK __BIT(27)
103 #define CAR_PLLU_BASE_CLKENABLE_48M __BIT(25)
104 #define CAR_PLLU_BASE_OVERRIDE __BIT(24)
105 #define CAR_PLLU_BASE_CLKENABLE_ICUSB __BIT(23)
106 #define CAR_PLLU_BASE_CLKENABLE_HSIC __BIT(22)
107 #define CAR_PLLU_BASE_CLKENABLE_USB __BIT(21)
114 #define CAR_PLLU_OUTA_OUT2_OVRRIDE __BIT(18)
115 #define CAR_PLLU_OUTA_OUT2_CLKEN __BIT(17)
116 #define CAR_PLLU_OUTA_OUT2_RSTN __BIT(16)
118 #define CAR_PLLU_OUTA_OUT1_OVRRIDE __BIT(2)
119 #define CAR_PLLU_OUTA_OUT1_CLKEN __BIT(1)
120 #define CAR_PLLU_OUTA_OUT1_RSTN __BIT(0)
123 #define CAR_PLLU_MISC_IDDQ __BIT(31)
124 #define CAR_PLLU_MISC_FREQLOCK __BIT(30)
125 #define CAR_PLLU_MISC_EN_LCKDET __BIT(29)
128 #define CAR_PLLU_MISC_KVCO __BIT(24)
132 #define CAR_PLLD_BASE_BYPASS __BIT(31)
133 #define CAR_PLLD_BASE_ENABLE __BIT(30)
134 #define CAR_PLLD_BASE_REF_DIS __BIT(29)
135 #define CAR_PLLD_BASE_LOCK __BIT(27)
136 #define CAR_PLLD_BASE_DSIA_CLK_SRC __BIT(25)
137 #define CAR_PLLD_BASE_CSI_CLK_SRC __BIT(23)
145 #define CAR_PLLX_BASE_BYPASS __BIT(31)
146 #define CAR_PLLX_BASE_ENABLE __BIT(30)
147 #define CAR_PLLX_BASE_REF_DIS __BIT(29)
148 #define CAR_PLLX_BASE_LOCK __BIT(27)
154 #define CAR_PLLX_MISC_FO_G_DISABLE __BIT(28)
156 #define CAR_PLLX_MISC_LOCK_ENABLE __BIT(18)
159 #define CAR_PLLE_BASE_ENABLE __BIT(31)
160 #define CAR_PLLE_BASE_LOCK_OVERRIDE __BIT(30)
161 #define CAR_PLLE_BASE_FDIV4B __BIT(29)
169 #define CAR_PLLE_MISC_ENABLE __BIT(15)
170 #define CAR_PLLE_MISC_IDDQ_SWCTL __BIT(14)
171 #define CAR_PLLE_MISC_IDDQ_OVERRIDE __BIT(13)
172 #define CAR_PLLE_MISC_LOCK __BIT(11)
173 #define CAR_PLLE_MISC_LOCK_ENABLE __BIT(9)
174 #define CAR_PLLE_MISC_PTS __BIT(8)
178 #define CAR_PLLE_MISC_KVCO __BIT(0)
181 #define CAR_PLLD2_BASE_BYPASS __BIT(31)
182 #define CAR_PLLD2_BASE_ENABLE __BIT(30)
183 #define CAR_PLLD2_BASE_REF_DIS __BIT(29)
184 #define CAR_PLLD2_BASE_FREQLOCK __BIT(28)
185 #define CAR_PLLD2_BASE_LOCK __BIT(27)
189 #define CAR_PLLD2_BASE_LOCK_OVERRIDE __BIT(24)
191 #define CAR_PLLD2_BASE_IDDQ __BIT(18)
192 #define CAR_PLLD2_BASE_PTS __BIT(16)
197 #define CAR_PLLD2_MISC_LOCK_ENABLE __BIT(30)
199 #define CAR_PLLD2_MISC_KVCO __BIT(24)
249 #define CAR_CLKSRC_UART_DIV_ENB __BIT(24)
305 #define CAR_DEV_L_CACHE2 __BIT(31)
306 #define CAR_DEV_L_I2S1 __BIT(30)
307 #define CAR_DEV_L_HOST1X __BIT(28)
308 #define CAR_DEV_L_DISP1 __BIT(27)
309 #define CAR_DEV_L_DISP2 __BIT(26)
310 #define CAR_DEV_L_ISP __BIT(23)
311 #define CAR_DEV_L_USBD __BIT(22)
312 #define CAR_DEV_L_VI __BIT(20)
313 #define CAR_DEV_L_I2S3 __BIT(18)
314 #define CAR_DEV_L_PWM __BIT(17)
315 #define CAR_DEV_L_SDMMC4 __BIT(15)
316 #define CAR_DEV_L_SDMMC1 __BIT(14)
317 #define CAR_DEV_L_I2C1 __BIT(12)
318 #define CAR_DEV_L_I2S2 __BIT(11)
319 #define CAR_DEV_L_SPDIF __BIT(10)
320 #define CAR_DEV_L_SDMMC2 __BIT(9)
321 #define CAR_DEV_L_GPIO __BIT(8)
322 #define CAR_DEV_L_UARTB __BIT(7)
323 #define CAR_DEV_L_UARTA __BIT(6)
324 #define CAR_DEV_L_TMR __BIT(5)
325 #define CAR_DEV_L_RTC __BIT(4)
326 #define CAR_DEV_L_ISPB __BIT(3)
327 #define CAR_DEV_L_TRIG_SYS __BIT(2)
328 #define CAR_DEV_L_COP __BIT(1)
329 #define CAR_DEV_L_CPU __BIT(0)
331 #define CAR_DEV_U_XUSB_DEV __BIT(31)
332 #define CAR_DEV_U_DEV1_OUT __BIT(30)
333 #define CAR_DEV_U_DEV2_OUT __BIT(29)
334 #define CAR_DEV_U_SUS_OUT __BIT(28)
335 #define CAR_DEV_U_MSENC __BIT(27)
336 #define CAR_DEV_U_XUSB_HOST __BIT(25)
337 #define CAR_DEV_U_CRAM2 __BIT(24)
338 #define CAR_DEV_U_IRAMD __BIT(23)
339 #define CAR_DEV_U_IRAMC __BIT(22)
340 #define CAR_DEV_U_IRAMB __BIT(21)
341 #define CAR_DEV_U_IRAMA __BIT(20)
342 #define CAR_DEV_U_TSEC __BIT(19)
343 #define CAR_DEV_U_DSIB __BIT(18)
344 #define CAR_DEV_U_I2C_SLOW __BIT(17)
345 #define CAR_DEV_U_DTV __BIT(15)
346 #define CAR_DEV_U_SOC_THERM __BIT(14)
347 #define CAR_DEV_U_PCIEXCLK __BIT(10)
348 #define CAR_DEV_U_CSITE __BIT(9)
349 #define CAR_DEV_U_AFI __BIT(8)
350 #define CAR_DEV_U_PCIE __BIT(6)
351 #define CAR_DEV_U_SDMMC3 __BIT(5)
352 #define CAR_DEV_U_SPI4 __BIT(4)
353 #define CAR_DEV_U_I2C3 __BIT(3)
354 #define CAR_DEV_U_UARTD __BIT(1)
356 #define CAR_DEV_H_BSEV __BIT(31)
357 #define CAR_DEV_H_USB2 __BIT(26)
358 #define CAR_DEV_H_EMC __BIT(25)
359 #define CAR_DEV_H_MIPI_CAL __BIT(24)
360 #define CAR_DEV_H_UARTC __BIT(23)
361 #define CAR_DEV_H_I2C2 __BIT(22)
362 #define CAR_DEV_H_CSI __BIT(20)
363 #define CAR_DEV_H_DSI __BIT(16)
364 #define CAR_DEV_H_I2C5 __BIT(15)
365 #define CAR_DEV_H_SPI3 __BIT(14)
366 #define CAR_DEV_H_SPI2 __BIT(12)
367 #define CAR_DEV_H_SPI1 __BIT(9)
368 #define CAR_DEV_H_KFUSE __BIT(8)
369 #define CAR_DEV_H_FUSE __BIT(7)
370 #define CAR_DEV_H_PMC __BIT(6)
371 #define CAR_DEV_H_STAT_MON __BIT(5)
372 #define CAR_DEV_H_APBDMA __BIT(2)
373 #define CAR_DEV_H_AHBDMA __BIT(1)
374 #define CAR_DEV_H_MEM __BIT(0)
376 #define CAR_DEV_V_HDA __BIT(29)
377 #define CAR_DEV_V_SATA __BIT(28)
378 #define CAR_DEV_V_SATA_OOB __BIT(27)
379 #define CAR_DEV_V_EXTPERIPH3 __BIT(26)
380 #define CAR_DEV_V_EXTPERIPH2 __BIT(25)
381 #define CAR_DEV_V_EXTPERIPH1 __BIT(24)
382 #define CAR_DEV_V_ACTMON __BIT(23)
383 #define CAR_DEV_V_SPDIF_DOUBLER __BIT(22)
384 #define CAR_DEV_V_ATOMICS __BIT(16)
385 #define CAR_DEV_V_HDA2CODEC_2X __BIT(15)
386 #define CAR_DEV_V_APB2APE __BIT(11)
387 #define CAR_DEV_V_AHUB __BIT(10)
388 #define CAR_DEV_V_I2C4 __BIT(7)
389 #define CAR_DEV_V_I2S5 __BIT(6)
390 #define CAR_DEV_V_I2S4 __BIT(5)
391 #define CAR_DEV_V_TSENSOR __BIT(4)
392 #define CAR_DEV_V_MSELECT __BIT(3)
393 #define CAR_DEV_V_CPULP __BIT(1)
394 #define CAR_DEV_V_CPUG __BIT(0)
396 #define CAR_DEV_W_MC1 __BIT(30)
397 #define CAR_DEV_W_EMC_DLL __BIT(29)
398 #define CAR_DEV_W_XUSB_SS __BIT(28)
399 #define CAR_DEV_W_DVFS __BIT(27)
400 #define CAR_DEV_W_ENTROPY __BIT(21)
401 #define CAR_DEV_W_DSIB_LP __BIT(20)
402 #define CAR_DEV_W_DSIA_LP __BIT(19)
403 #define CAR_DEV_W_CILEF __BIT(18)
404 #define CAR_DEV_W_CILCD __BIT(17)
405 #define CAR_DEV_W_CILAB __BIT(16)
406 #define CAR_DEV_W_XUSB __BIT(15)
407 #define CAR_DEV_W_XUSB_PADCTL __BIT(14)
408 #define CAR_DEV_W_MIPI_IOBIST __BIT(13)
409 #define CAR_DEV_W_SATA_IOBIST __BIT(12)
410 #define CAR_DEV_W_EMC_IOBIST __BIT(10)
411 #define CAR_DEV_W_PCIE2_IOBIST __BIT(9)
412 #define CAR_DEV_W_CEC __BIT(8)
413 #define CAR_DEV_W_PCIERX5 __BIT(7)
414 #define CAR_DEV_W_PCIERX4 __BIT(6)
415 #define CAR_DEV_W_PCIERX3 __BIT(5)
416 #define CAR_DEV_W_PCIERX2 __BIT(4)
417 #define CAR_DEV_W_PCIERX1 __BIT(3)
418 #define CAR_DEV_W_PCIERX0 __BIT(2)
419 #define CAR_DEV_W_SATACOLD __BIT(1)
420 #define CAR_DEV_W_HDA2HDMICODEC __BIT(0)
422 #define CAR_DEV_X_PLLG_REF __BIT(29)
423 #define CAR_DEV_X_PLLA_ADSP __BIT(28)
424 #define CAR_DEV_X_PLLP_ADSP __BIT(27)
425 #define CAR_DEV_X_HPLL_ADSP __BIT(26)
426 #define CAR_DEV_X_DBGAPB __BIT(25)
427 #define CAR_DEV_X_GPU __BIT(24)
428 #define CAR_DEV_X_SOR1 __BIT(23)
429 #define CAR_DEV_X_SOR0 __BIT(22)
430 #define CAR_DEV_X_DPAUX __BIT(21)
431 #define CAR_DEV_X_VIC __BIT(18)
432 #define CAR_DEV_X_UART_FST_MIPI_CAL __BIT(17)
433 #define CAR_DEV_X_EMC_DLL __BIT(14)
434 #define CAR_DEV_X_VIM2_CLK __BIT(11)
435 #define CAR_DEV_X_MC_BBC __BIT(10)
436 #define CAR_DEV_X_MC_CPU __BIT(9)
437 #define CAR_DEV_X_MC_CBPA __BIT(8)
438 #define CAR_DEV_X_MC_CAPA __BIT(7)
439 #define CAR_DEV_X_I2C6 __BIT(6)
440 #define CAR_DEV_X_CAM_MCLK2 __BIT(5)
441 #define CAR_DEV_X_CAM_MCLK __BIT(4)
442 #define CAR_DEV_X_ETR __BIT(3)
443 #define CAR_DEV_X_SPARE __BIT(0)
445 #define CAR_DEV_Y_PLLP_OUT_CPU __BIT(31)
446 #define CAR_DEV_Y_SOR_SAFE __BIT(30)
447 #define CAR_DEV_Y_IQC1 __BIT(29)
448 #define CAR_DEV_Y_IQC2 __BIT(28)
449 #define CAR_DEV_Y_NVENC __BIT(27)
450 #define CAR_DEV_Y_ADSPNEON __BIT(26)
451 #define CAR_DEV_Y_ADSPSCU __BIT(25)
452 __BIT(24)
453 #define CAR_DEV_Y_ADSPDBG __BIT(23)
454 #define CAR_DEV_Y_ADSPPERIPH __BIT(22)
455 #define CAR_DEV_Y_ADSPINTF __BIT(21)
456 #define CAR_DEV_Y_UARTAPE __BIT(20)
457 #define CAR_DEV_Y_QSPI __BIT(19)
458 #define CAR_DEV_Y_USB2_TRK __BIT(18)
459 #define CAR_DEV_Y_HSIC_TRK __BIT(17)
460 #define CAR_DEV_Y_VI_I2C __BIT(16)
461 #define CAR_DEV_Y_DPAUX __BIT(15)
462 #define CAR_DEV_Y_TSECB __BIT(14)
463 #define CAR_DEV_Y_PEX_USB_UPHY __BIT(13)
464 #define CAR_DEV_Y_SATA_USB_UPHY __BIT(12)
465 #define CAR_DEV_Y_MAUD __BIT(10)
466 #define CAR_DEV_Y_MC_CCPA __BIT(9)
467 #define CAR_DEV_Y_MC_CDPA __BIT(8)
468 #define CAR_DEV_Y_ADSP __BIT(7)
469 #define CAR_DEV_Y_APE __BIT(6)
470 #define CAR_DEV_Y_DMIC3 __BIT(5)
471 #define CAR_DEV_Y_AXIAP __BIT(4)
472 #define CAR_DEV_Y_NVJPG __BIT(3)
473 #define CAR_DEV_Y_NVDEC __BIT(2)
474 #define CAR_DEV_Y_SDMMC_LEGACY_TM __BIT(1)
475 #define CAR_DEV_Y_SPARE1 __BIT(0)
504 #define CAR_CLKSRC_SATA_AUX_CLK_ENB __BIT(24)
515 #define CAR_UTMIP_PLL_CFG1_PLLU_POWERUP __BIT(17)
516 #define CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN __BIT(16)
517 #define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP __BIT(15)
518 #define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN __BIT(14)
522 #define CAR_UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN __BIT(30)
523 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_D_POWERUP __BIT(25)
524 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_D_POWERDOWN __BIT(24)
527 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP __BIT(5)
528 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN __BIT(4)
529 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP __BIT(3)
530 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN __BIT(2)
531 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP __BIT(1)
532 #define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN __BIT(0)
535 #define CAR_PLLE_AUX_SS_SEQ_INCLUDE __BIT(31)
536 #define CAR_PLLE_AUX_REF_SEL_PLLREFE __BIT(28)
538 #define CAR_PLLE_AUX_SEQ_START_STATE __BIT(25)
539 #define CAR_PLLE_AUX_SEQ_ENABLE __BIT(24)
542 #define CAR_PLLE_AUX_FAST_PT __BIT(7)
543 #define CAR_PLLE_AUX_SS_SWCTL __BIT(6)
544 #define CAR_PLLE_AUX_CONFIG_SWCTL __BIT(5)
545 #define CAR_PLLE_AUX_ENABLE_SWCTL __BIT(4)
546 #define CAR_PLLE_AUX_USE_LOCKDET __BIT(3)
547 #define CAR_PLLE_AUX_REF_SRC __BIT(2)
548 #define CAR_PLLE_AUX_CML1_OEN __BIT(1)
549 #define CAR_PLLE_AUX_CML0_OEN __BIT(0)
553 #define CAR_SATA_PLL_CFG0_SEQ_START_STATE __BIT(25)
554 #define CAR_SATA_PLL_CFG0_SEQ_ENABLE __BIT(24)
555 #define CAR_SATA_PLL_CFG0_SEQ_PADPLL_SLEEP_IDDQ __BIT(13)
556 #define CAR_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE __BIT(7)
557 #define CAR_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE __BIT(6)
558 #define CAR_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
559 #define CAR_SATA_PLL_CFG0_SEQ_IN_SWCTL __BIT(4)
560 #define CAR_SATA_PLL_CFG0_PADPLL_USE_LOCKDET __BIT(2)
561 #define CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1)
562 #define CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL __BIT(0)
571 #define CAR_UTMIP_PLL_CFG3_REF_SRC_SEL __BIT(26)
572 #define CAR_UTMIP_PLL_CFG3_REF_DIS __BIT(25)
573 #define CAR_UTMIP_PLL_CFG3_PTS __BIT(24)
577 #define CAR_PLLREFE_BASE_BYPASS __BIT(31)
578 #define CAR_PLLREFE_BASE_ENABLE __BIT(30)
579 #define CAR_PLLREFE_BASE_REF_DIS __BIT(29)
581 #define CAR_PLLREFE_BASE_KVCO __BIT(26)
587 #define CAR_PLLREFE_MISC_LOCK_ENABLE __BIT(30)
588 #define CAR_PLLREFE_MISC_LOCK_OVERRIDE __BIT(29)
589 #define CAR_PLLREFE_MISC_FREQLOCK __BIT(28)
590 #define CAR_PLLREFE_MISC_LOCK __BIT(27)
592 #define CAR_PLLREFE_MISC_IDDQ __BIT(24)
597 #define CAR_XUSBIO_PLL_CFG0_SEQ_START_STATE __BIT(25)
598 #define CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE __BIT(24)
599 #define CAR_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ __BIT(13)
600 #define CAR_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET __BIT(6)
601 #define CAR_XUSBIO_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
602 #define CAR_XUSBIO_PLL_CFG0_SEQ_IN_SWCTL __BIT(4)
603 #define CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_OVERRIDE __BIT(3)
604 #define CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL __BIT(2)
605 #define CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1)
606 #define CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL __BIT(0)
609 #define CAR_UTMIPLL_HW_PWRDN_CFG0_LOCK __BIT(31)
611 #define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE __BIT(25)
612 #define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE __BIT(24)
613 #define CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE __BIT(7)
614 #define CAR_UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET __BIT(6)
615 #define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
616 #define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL __BIT(4)
617 #define CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_OVERRIDE __BIT(3)
618 #define CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL __BIT(2)
619 #define CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE __BIT(1)
620 #define CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL __BIT(0)
623 #define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE __BIT(28)
625 #define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_START_STATE __BIT(25)
626 #define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_ENABLE __BIT(24)
627 #define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT __BIT(7)
628 #define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_LOCKDET __BIT(6)
629 #define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
630 #define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_IN_SWCTL __BIT(4)
631 #define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_OVERRIDE_VALUE __BIT(3)
632 #define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL __BIT(2)
633 #define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL __BIT(0)
655 #define CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS __BIT(25)
656 #define CAR_CLKSRC_XUSB_SS_SS_CLK_BYPASS __BIT(24)
Indexes created Wed Oct 22 13:09:56 GMT 2025