Lines Matching defs:tegra_crtc
279 struct tegra_crtc *crtc;
370 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
376 if (tegra_crtc->enabled == false)
381 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG);
384 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt);
386 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
388 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
406 handle, tegra_crtc->index);
440 struct drm_gem_cma_object *cursor_obj = tegra_crtc->cursor_obj;
448 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_HI_REG,
453 DC_READ(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG);
455 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_START_ADDR_REG, cfg);
458 cfg = DC_READ(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG);
466 DC_WRITE(tegra_crtc, DC_DISP_BLEND_CURSOR_CONTROL_REG, cfg);
469 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG,
470 __SHIFTIN(tegra_crtc->cursor_x, DC_DISP_CURSOR_POSITION_H) |
471 __SHIFTIN(tegra_crtc->cursor_y, DC_DISP_CURSOR_POSITION_V));
474 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
476 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
480 opt = DC_READ(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG);
483 DC_WRITE(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG, opt);
486 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
488 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
497 while (DC_READ(tegra_crtc, DC_CMD_STATE_CONTROL_REG) &
512 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
514 tegra_crtc->cursor_x = x & 0x3fff;
515 tegra_crtc->cursor_y = y & 0x3fff;
517 DC_WRITE(tegra_crtc, DC_DISP_CURSOR_POSITION_REG,
522 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
524 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
533 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
535 if (tegra_crtc
536 intr_disestablish(tegra_crtc->ih);
538 drm_gem_cma_free_object(&tegra_crtc->cursor_obj->base);
539 bus_space_unmap(tegra_crtc->bst, tegra_crtc->bsh, tegra_crtc->size);
540 kmem_free(tegra_crtc, sizeof(*tegra_crtc));
546 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
552 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG,
556 DC_SET_CLEAR(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG,
574 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
583 DC_WRITE(tegra_crtc, DC_WINC_A_COLOR_DEPTH_REG,
588 DC_WRITE(tegra_crtc, DC_WINC_A_BYTE_SWAP_REG,
593 DC_WRITE(tegra_crtc, DC_WINC_A_H_INITIAL_DDA_REG, 0);
594 DC_WRITE(tegra_crtc, DC_WINC_A_V_INITIAL_DDA_REG, 0);
595 DC_WRITE(tegra_crtc, DC_WINC_A_DDA_INCREMENT_REG, 0x10001000);
598 DC_WRITE(tegra_crtc, DC_WINC_A_POSITION_REG,
601 DC_WRITE(tegra_crtc, DC_WINC_A_SIZE_REG,
604 DC_WRITE(tegra_crtc, DC_WINC_A_PRESCALED_SIZE_REG,
608 DC_WRITE(tegra_crtc, DC_WINC_A_LINE_STRIDE_REG,
615 DC_WRITE(tegra_crtc, DC_WINC_A_WIN_OPTIONS_REG,
619 DC_WRITE(tegra_crtc, DC_DISP_DISP_TIMING_OPTIONS_REG,
621 DC_WRITE(tegra_crtc, DC_DISP_DISP_COLOR_CONTROL_REG,
624 DC_WRITE(tegra_crtc, DC_DISP_DISP_SIGNAL_OPTIONS0_REG,
626 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_CONTROL_REG,
633 DC_WRITE(tegra_crtc, DC_DISP_H_PULSE2_POSITION_A_REG,
638 const u_int parent_rate = clk_get_rate(tegra_crtc->clk_parent);
640 DC_WRITE(tegra_crtc, DC_DISP_DISP_CLOCK_CONTROL_REG,
645 DC_WRITE(tegra_crtc, DC_DISP_REF_TO_SYNC_REG,
648 DC_WRITE(tegra_crtc, DC_DISP_SYNC_WIDTH_REG,
651 DC_WRITE(tegra_crtc, DC_DISP_BACK_PORCH_REG,
654 DC_WRITE(tegra_crtc, DC_DISP_FRONT_PORCH_REG,
657 DC_WRITE(tegra_crtc, DC_DISP_DISP_ACTIVE_REG,
668 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
676 DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_HI_REG, (paddr >> 32) & 3);
677 DC_WRITE(tegra_crtc, DC_WINBUF_A_START_ADDR_REG, paddr & 0xffffffff);
680 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_H_OFFSET_REG, x);
681 DC_WRITE(tegra_crtc, DC_WINBUF_A_ADDR_V_OFFSET_REG, y);
684 DC_WRITE(tegra_crtc, DC_WINBUF_A_SURFACE_KIND_REG,
695 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
700 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
702 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
712 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
717 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
719 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
733 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
736 DC_WRITE(tegra_crtc, DC_CMD_STATE_ACCESS_REG, 0);
739 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_WINDOW_HEADER_REG,
746 struct tegra_crtc *tegra_crtc = to_tegra_crtc(crtc);
749 DC_WRITE(tegra_crtc, DC_CMD_DISPLAY_COMMAND_REG,
754 DC_SET_CLEAR(tegra_crtc, DC_CMD_DISPLAY_POWER_CONTROL_REG,
765 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
768 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
772 tegra_crtc->enabled = true;
904 struct tegra_crtc *tegra_crtc = to_tegra_crtc(encoder->crtc);
966 input_ctrl = __SHIFTIN(tegra_crtc->index,
1136 DC_SET_CLEAR(tegra_crtc, DC_DISP_DISP_WIN_OPTIONS_REG,
1140 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
1143 DC_WRITE(tegra_crtc, DC_CMD_STATE_CONTROL_REG,
1285 struct tegra_crtc *tegra_crtc = priv;
1286 struct drm_device *ddev = tegra_crtc->base.dev;
1290 const uint32_t status = DC_READ(tegra_crtc, DC_CMD_INT_STATUS_REG);
1293 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK);
1294 atomic_inc_32(&sc->sc_vbl_received[tegra_crtc->index]);
1295 drm_handle_vblank(ddev, tegra_crtc->index);
1316 struct tegra_crtc *tegra_crtc = NULL;
1321 tegra_crtc = to_tegra_crtc(iter);
1325 if (tegra_crtc == NULL)
1328 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, DC_CMD_INT_V_BLANK, 0);
1336 struct tegra_crtc *tegra_crtc = NULL;
1341 tegra_crtc = to_tegra_crtc(iter);
1345 if (tegra_crtc == NULL)
1348 DC_SET_CLEAR(tegra_crtc, DC_CMD_INT_MASK_REG, 0, DC_CMD_INT_V_BLANK);
1349 DC_WRITE(tegra_crtc, DC_CMD_INT_STATUS_REG, DC_CMD_INT_V_BLANK);
Indexes created Wed Oct 01 15:09:59 GMT 2025