Lines Matching defs:bank
139 #define GPIO_WRITE(bank, reg, val) \
140 bus_space_write_4((bank)->bank_sc->sc_bst, \
141 (bank)->bank_sc->sc_bsh, \
142 (bank)->bank_pb->base + (reg), (val))
143 #define GPIO_READ(bank, reg) \
144 bus_space_read_4((bank)->bank_sc->sc_bst, \
145 (bank)->bank_sc->sc_bsh, \
146 (bank)->bank_pb->base + (reg))
202 struct tegra_gpio_bank *bank = &sc->sc_banks[bankno];
206 bank->bank_sc = sc;
207 bank->bank_pb = &tegra_gpio_pinbanks[bankno];
208 bank->bank_gc.gp_cookie = bank;
209 bank->bank_gc.gp_pin_read = tegra_gpio_pin_read;
210 bank->bank_gc.gp_pin_write = tegra_gpio_pin_write;
211 bank->bank_gc.gp_pin_ctl = tegra_gpio_pin_ctl;
213 const uint32_t cnf = GPIO_READ(bank, GPIO_CNF_REG);
215 for (pin = 0; pin < __arraycount(bank->bank_pins); pin++) {
216 bank->bank_pins[pin].pin_num = pin;
220 bank->bank_pins[pin].pin_caps =
223 bank->bank_pins[pin].pin_state =
224 tegra_gpio_pin_read(bank, pin);
228 gba.gba_gc = &bank->bank_gc;
229 gba.gba_pins = bank->bank_pins;
230 gba.gba_npins = __arraycount(bank->bank_pins);
232 bank->bank_dev =
240 struct tegra_gpio_bank *bank = gba->gba_gc->gp_cookie;
241 const char *bankname = bank->bank_pb->name;
254 struct tegra_gpio_bank *bank = priv;
256 const uint32_t v = GPIO_READ(bank, GPIO_IN_REG);
264 struct tegra_gpio_bank *bank = priv;
269 GPIO_WRITE(bank, GPIO_MSK_OUT_REG, v);
275 struct tegra_gpio_bank *bank = priv;
280 GPIO_WRITE(bank, GPIO_MSK_OE_REG, v);
284 GPIO_WRITE(bank, GPIO_MSK_OE_REG, v);
298 const u_int bank = be32toh(gpio[1]) >> 3;
302 if (bank >= __arraycount(tegra_gpio_pinbanks) || pin > 8)
306 gbank.bank_pb = &tegra_gpio_pinbanks[bank];
389 struct tegra_gpio_bank bank;
398 bank.bank_sc = device_private(dev);
399 bank.bank_pb = tegra_gpio_pin_lookup(pinname, &pin);
400 if (bank.bank_pb == NULL)
403 const uint32_t cnf = GPIO_READ(&bank, GPIO_CNF_REG);
405 GPIO_WRITE(&bank, GPIO_CNF_REG, cnf | __BIT(pin));
408 gpin->pin_bank = bank;
Indexes created Wed Oct 01 07:09:59 GMT 2025