Lines Matching defs:cfg
129 uint32_t cfg;
133 cfg = PINMUX_READ(sc, pin_def->tpp_reg);
134 const uint32_t ocfg = cfg;
138 cfg &= ~PINMUX_PM;
139 cfg |= __SHIFTIN(func, PINMUX_PM);
142 cfg &= ~PINMUX_PUPD;
143 cfg |= __SHIFTIN(val, PINMUX_PUPD);
146 cfg &= ~PINMUX_TRISTATE;
147 cfg |= __SHIFTIN(val, PINMUX_TRISTATE);
150 cfg &= ~PINMUX_E_OD;
151 cfg |= __SHIFTIN(val, PINMUX_E_OD);
154 cfg &= ~PINMUX_LOCK;
155 cfg |= __SHIFTIN(val, PINMUX_LOCK);
158 cfg &= ~PINMUX_E_IO_HV;
159 cfg |= __SHIFTIN(val, PINMUX_E_IO_HV);
162 cfg &= ~PINMUX_E_HSM;
163 cfg |= __SHIFTIN(val, PINMUX_E_HSM);
166 cfg &= ~PINMUX_E_SCHMT;
167 cfg |= __SHIFTIN(val, PINMUX_E_SCHMT);
170 cfg &= ~PINMUX_DRV_TYPE;
171 cfg |= __SHIFTIN(val, PINMUX_DRV_TYPE);
174 pin_def->tpp_name, ocfg, cfg);
175 if (cfg != ocfg)
176 PINMUX_WRITE(sc, pin_def->tpp_reg, cfg);
179 cfg = PADCTRL_READ(sc, pin_def->tpp_reg);
180 const uint32_t ocfg = cfg;
183 cfg &= ~pin_def->tpp_dg.drvdn_mask;
184 cfg |= __SHIFTIN(val, pin_def->tpp_dg.drvdn_mask);
187 cfg &= ~pin_def->tpp_dg.drvup_mask;
188 cfg |= __SHIFTIN(val, pin_def->tpp_dg.drvup_mask);
191 cfg &= ~pin_def->tpp_dg.slwrf_mask;
192 cfg |= __SHIFTIN(val, pin_def->tpp_dg.slwrf_mask);
195 cfg &= ~pin_def->tpp_dg.slwrr_mask;
196 cfg |= __SHIFTIN(val, pin_def->tpp_dg.slwrr_mask);
200 pin_def->tpp_name, ocfg, cfg);
201 if (cfg != ocfg)
202 PADCTRL_WRITE(sc, pin_def->tpp_reg, cfg);
Indexes created Wed Oct 01 13:09:50 GMT 2025