Lines Matching refs:CLK_DIV
1015 CLK_DIV("periph_clk2", "periph_clk2_sel", CBCDR, PERIPH_CLK2_PODF),
1016 CLK_DIV("periph2_clk2", "periph2_clk2_sel", CBCDR, PERIPH2_CLK2_PODF),
1018 CLK_DIV("ipg", "ahb", CBCDR, IPG_PODF),
1019 CLK_DIV("gpu_core_podf", "gpu_core_sel", CBCMR, GPU3D_SHADER_PODF),
1020 CLK_DIV("gpu_axi_podf", "gpu_axi_sel", CBCMR, GPU3D_CORE_PODF),
1021 CLK_DIV("lcdif1_podf", "lcdif1_pred", CBCMR, GPU2D_CORE_CLK_PODF),
1022 CLK_DIV("esai_pred", "esai_sel", CS1CDR, ESAI_CLK_PRED),
1023 CLK_DIV("esai_podf", "esai_pred", CS1CDR, ESAI_CLK_PODF),
1024 CLK_DIV("spdif_pred", "spdif_sel", CDCDR, SPDIF0_CLK_PRED),
1025 CLK_DIV("spdif_podf", "spdif_pred", CDCDR, SPDIF0_CLK_PODF),
1026 CLK_DIV("audio_pred", "audio_sel", CDCDR, SPDIF1_CLK_PRED),
1027 CLK_DIV("audio_podf", "audio_pred", CDCDR, SPDIF1_CLK_PODF),
1028 CLK_DIV("vid_podf", "vid_sel", CSCMR2, VID_CLK_PODF),
1029 CLK_DIV("can_podf", "can_sel", CSCMR2, CAN_CLK_PODF),
1030 CLK_DIV("display_podf", "display_sel", CSCDR3, IPU2_HSP_PODF),
1031 CLK_DIV("csi_podf", "csi_sel", CSCDR3, IPU1_HSP_PODF),
1032 CLK_DIV("enet_podf", "enet_pre_sel", CHSCCDR, IPU1_DI1_PODF),
1033 CLK_DIV("m4_podf", "m4_sel", CHSCCDR, IPU1_DI0_PODF),
1034 CLK_DIV("ecspi_podf", "ecspi_sel", CSCDR2, ECSPI_CLK_PODF),
1035 CLK_DIV("lcdif1_pred", "lcdif1_pre_sel", CSCDR2, IPU2_DI1_PODF),
1036 CLK_DIV("lcdif2_pred", "lcdif2_pre_sel", CSCDR2, IPU2_DI0_PODF),
1037 CLK_DIV("ssi1_pred", "ssi1_sel", CS1CDR, SSI1_CLK_PRED),
1038 CLK_DIV("ssi1_podf", "ssi1_pred", CS1CDR, SSI1_CLK_PODF),
1039 CLK_DIV("ssi2_pred", "ssi2_sel", CS2CDR, SSI2_CLK_PRED),
1040 CLK_DIV("ssi2_podf", "ssi2_pred", CS2CDR, SSI2_CLK_PODF),
1041 CLK_DIV("ssi3_pred", "ssi3_sel", CS1CDR, SSI3_CLK_PRED),
1042 CLK_DIV("ssi3_podf", "ssi3_pred", CS1CDR, SSI3_CLK_PODF),
1043 CLK_DIV("usdhc1_podf", "usdhc1_sel", CSCDR1, USDHC1_PODF),
1044 CLK_DIV("usdhc2_podf", "usdhc2_sel", CSCDR1, USDHC2_PODF),
1045 CLK_DIV("usdhc3_podf", "usdhc3_sel", CSCDR1, USDHC3_PODF),
1046 CLK_DIV("usdhc4_podf", "usdhc4_sel", CSCDR1, USDHC4_PODF),
1047 CLK_DIV("uart_podf", "uart_sel", CSCDR1, UART_CLK_PODF),
1048 CLK_DIV("qspi2_pred", "qspi2_sel", CS2CDR, ENFC_CLK_PRED),
1049 CLK_DIV("qspi2_podf", "qspi2_pred", CS2CDR, ENFC_CLK_PODF),
1050 CLK_DIV("cko1_podf", "cko1_sel", CCOSR, CLKO1_DIV),
1051 CLK_DIV("cko2_podf", "cko2_sel", CCOSR, CLKO2_DIV),
1052 CLK_DIV("qspi1_podf", "qspi1_sel", CSCMR1, QSPI1_PODF),
1053 CLK_DIV("eim_slow_podf", "eim_slow_sel", CSCMR1, ACLK_EIM_SLOW_PODF),
1054 CLK_DIV("lcdif2_podf", "lcdif2_pred", CSCMR1, ACLK_PODF),
1055 CLK_DIV("perclk", "perclk_sel", CSCMR1, PERCLK_PODF),
Indexes created Tue Oct 21 07:10:13 GMT 2025