Lines Matching refs:__BITS
85 { RK3588_PMU1_IOC_REG + 0x0010, __BITS(3,0) },
86 { RK3588_PMU1_IOC_REG + 0x0010, __BITS(7,4) },
87 { RK3588_PMU1_IOC_REG + 0x0010, __BITS(11,8) },
88 { RK3588_PMU1_IOC_REG + 0x0010, __BITS(15,12) },
89 { RK3588_PMU1_IOC_REG + 0x0014, __BITS(3,0) },
90 { RK3588_PMU1_IOC_REG + 0x0014, __BITS(7,4) },
91 { RK3588_PMU1_IOC_REG + 0x0014, __BITS(11,8) },
92 { RK3588_PMU1_IOC_REG + 0x0014, __BITS(15,12) },
94 { RK3588_PMU1_IOC_REG + 0x0018, __BITS(3,0) },
95 { RK3588_PMU1_IOC_REG + 0x0018, __BITS(7,4) },
96 { RK3588_PMU1_IOC_REG + 0x0018, __BITS(11,8) },
97 { RK3588_PMU1_IOC_REG + 0x0018, __BITS(15,12) },
98 { RK3588_PMU2_IOC_REG + 0x0014, __BITS(3,0) },
99 { RK3588_PMU2_IOC_REG + 0x0014, __BITS(7,4) },
100 { RK3588_PMU2_IOC_REG + 0x0014, __BITS(11,8) },
101 { RK3588_PMU2_IOC_REG + 0x0014, __BITS(15,12) },
103 { RK3588_PMU2_IOC_REG + 0x0018, __BITS(3,0) },
104 { RK3588_PMU2_IOC_REG + 0x0018, __BITS(7,4) },
105 { RK3588_PMU2_IOC_REG + 0x0018, __BITS(11,8) },
106 { RK3588_PMU2_IOC_REG + 0x0018, __BITS(15,12) },
107 { RK3588_PMU2_IOC_REG + 0x001c, __BITS(3,0) },
108 { RK3588_PMU2_IOC_REG + 0x001c, __BITS(7,4) },
109 { RK3588_PMU2_IOC_REG + 0x001c, __BITS(11,8) },
110 { RK3588_PMU2_IOC_REG + 0x001c, __BITS(15,12) },
112 { RK3588_PMU2_IOC_REG + 0x0020, __BITS(3,0) },
113 { RK3588_PMU2_IOC_REG + 0x0020, __BITS(7,4) },
114 { RK3588_PMU2_IOC_REG + 0x0020, __BITS(11,8) },
115 { RK3588_PMU2_IOC_REG + 0x0020, __BITS(15,12) },
116 { RK3588_PMU2_IOC_REG + 0x0024, __BITS(3,0) },
117 { RK3588_PMU2_IOC_REG + 0x0024, __BITS(7,4) },
118 { RK3588_PMU2_IOC_REG + 0x0024, __BITS(11,8) },
119 { RK3588_PMU2_IOC_REG + 0x0024, __BITS(15,12) },
122 { RK3588_VCCIO1_4_IOC_REG + 0x0020, __BITS(3,0) },
123 { RK3588_VCCIO1_4_IOC_REG + 0x0020, __BITS(7,4) },
124 { RK3588_VCCIO1_4_IOC_REG + 0x0020, __BITS(11,8) },
125 { RK3588_VCCIO1_4_IOC_REG + 0x0020, __BITS(15,12) },
126 { RK3588_VCCIO1_4_IOC_REG + 0x0024, __BITS(3,0) },
127 { RK3588_VCCIO1_4_IOC_REG + 0x0024, __BITS(7,4) },
128 { RK3588_VCCIO1_4_IOC_REG + 0x0024, __BITS(11,8) },
129 { RK3588_VCCIO1_4_IOC_REG + 0x0024, __BITS(15,12) },
131 { RK3588_VCCIO1_4_IOC_REG + 0x0028, __BITS(3,0) },
132 { RK3588_VCCIO1_4_IOC_REG + 0x0028, __BITS(7,4) },
133 { RK3588_VCCIO1_4_IOC_REG + 0x0028, __BITS(11,8) },
134 { RK3588_VCCIO1_4_IOC_REG + 0x0028, __BITS(15,12) },
135 { RK3588_VCCIO1_4_IOC_REG + 0x002c, __BITS(3,0) },
136 { RK3588_VCCIO1_4_IOC_REG + 0x002c, __BITS(7,4) },
137 { RK3588_VCCIO1_4_IOC_REG + 0x002c, __BITS(11,8) },
138 { RK3588_VCCIO1_4_IOC_REG + 0x002c, __BITS(15,12) },
140 { RK3588_VCCIO1_4_IOC_REG + 0x0030, __BITS(3,0) },
141 { RK3588_VCCIO1_4_IOC_REG + 0x0030, __BITS(7,4) },
142 { RK3588_VCCIO1_4_IOC_REG + 0x0030, __BITS(11,8) },
143 { RK3588_VCCIO1_4_IOC_REG + 0x0030, __BITS(15,12) },
144 { RK3588_VCCIO1_4_IOC_REG + 0x0034, __BITS(3,0) },
145 { RK3588_VCCIO1_4_IOC_REG + 0x0034, __BITS(7,4) },
146 { RK3588_VCCIO1_4_IOC_REG + 0x0034, __BITS(11,8) },
147 { RK3588_VCCIO1_4_IOC_REG + 0x0034, __BITS(15,12) },
149 { RK3588_VCCIO1_4_IOC_REG + 0x0038, __BITS(3,0) },
150 { RK3588_VCCIO1_4_IOC_REG + 0x0038, __BITS(7,4) },
151 { RK3588_VCCIO1_4_IOC_REG + 0x0038, __BITS(11,8) },
152 { RK3588_VCCIO1_4_IOC_REG + 0x0038, __BITS(15,12) },
153 { RK3588_VCCIO1_4_IOC_REG + 0x003c, __BITS(3,0) },
154 { RK3588_VCCIO1_4_IOC_REG + 0x003c, __BITS(7,4) },
155 { RK3588_VCCIO1_4_IOC_REG + 0x003c, __BITS(11,8) },
156 { RK3588_VCCIO1_4_IOC_REG + 0x003c, __BITS(15,12) },
159 { RK3588_EMMC_IOC_REG + 0x0040, __BITS(3,0) },
160 { RK3588_EMMC_IOC_REG + 0x0040, __BITS(7,4) },
161 { RK3588_EMMC_IOC_REG + 0x0040, __BITS(11,8) },
162 { RK3588_EMMC_IOC_REG + 0x0040, __BITS(15,12) },
163 { RK3588_VCCIO3_5_IOC_REG + 0x0044, __BITS(3,0) },
164 { RK3588_VCCIO3_5_IOC_REG + 0x0044, __BITS(7,4) },
165 { RK3588_VCCIO3_5_IOC_REG + 0x0044, __BITS(11,8) },
166 { RK3588_VCCIO3_5_IOC_REG + 0x0044, __BITS(15,12) },
168 { RK3588_VCCIO3_5_IOC_REG + 0x0048, __BITS(3,0) },
169 { RK3588_VCCIO3_5_IOC_REG + 0x0048, __BITS(7,4) },
170 { RK3588_VCCIO3_5_IOC_REG + 0x0048, __BITS(11,8) },
171 { RK3588_VCCIO3_5_IOC_REG + 0x0048, __BITS(15,12) },
172 { RK3588_VCCIO3_5_IOC_REG + 0x004c, __BITS(3,0) },
173 { RK3588_VCCIO3_5_IOC_REG + 0x004c, __BITS(7,4) },
174 { RK3588_VCCIO3_5_IOC_REG + 0x004c, __BITS(11,8) },
175 { RK3588_VCCIO3_5_IOC_REG + 0x004c, __BITS(15,12) },
177 { RK3588_VCCIO3_5_IOC_REG + 0x0050, __BITS(3,0) },
178 { RK3588_VCCIO3_5_IOC_REG + 0x0050, __BITS(7,4) },
179 { RK3588_VCCIO3_5_IOC_REG + 0x0050, __BITS(11,8) },
180 { RK3588_VCCIO3_5_IOC_REG + 0x0050, __BITS(15,12) },
181 { RK3588_VCCIO3_5_IOC_REG + 0x0054, __BITS(3,0) },
182 { RK3588_VCCIO3_5_IOC_REG + 0x0054, __BITS(7,4) },
183 { RK3588_VCCIO3_5_IOC_REG + 0x0054, __BITS(11,8) },
184 { RK3588_VCCIO3_5_IOC_REG + 0x0054, __BITS(15,12) },
186 { RK3588_EMMC_IOC_REG + 0x0058, __BITS(3,0) },
187 { RK3588_EMMC_IOC_REG + 0x0058, __BITS(7,4) },
188 { RK3588_EMMC_IOC_REG + 0x0058, __BITS(11,8) },
189 { RK3588_EMMC_IOC_REG + 0x0058, __BITS(15,12) },
190 { RK3588_EMMC_IOC_REG + 0x005c, __BITS(3,0) },
191 { RK3588_EMMC_IOC_REG + 0x005c, __BITS(7,4) },
192 { RK3588_EMMC_IOC_REG + 0x005c, __BITS(11,8) },
193 { RK3588_EMMC_IOC_REG + 0x005c, __BITS(15,12) },
196 { RK3588_VCCIO3_5_IOC_REG + 0x0060, __BITS(3,0) },
197 { RK3588_VCCIO3_5_IOC_REG + 0x0060, __BITS(7,4) },
198 { RK3588_VCCIO3_5_IOC_REG + 0x0060, __BITS(11,8) },
199 { RK3588_VCCIO3_5_IOC_REG + 0x0060, __BITS(15,12) },
200 { RK3588_VCCIO3_5_IOC_REG + 0x0064, __BITS(3,0) },
201 { RK3588_VCCIO3_5_IOC_REG + 0x0064, __BITS(7,4) },
202 { RK3588_VCCIO3_5_IOC_REG + 0x0064, __BITS(11,8) },
203 { RK3588_VCCIO3_5_IOC_REG + 0x0064, __BITS(15,12) },
205 { RK3588_VCCIO3_5_IOC_REG + 0x0068, __BITS(3,0) },
206 { RK3588_VCCIO3_5_IOC_REG + 0x0068, __BITS(7,4) },
207 { RK3588_VCCIO3_5_IOC_REG + 0x0068, __BITS(11,8) },
208 { RK3588_VCCIO3_5_IOC_REG + 0x0068, __BITS(15,12) },
209 { RK3588_VCCIO3_5_IOC_REG + 0x006c, __BITS(3,0) },
210 { RK3588_VCCIO3_5_IOC_REG + 0x006c, __BITS(7,4) },
211 { RK3588_VCCIO3_5_IOC_REG + 0x006c, __BITS(11,8) },
212 { RK3588_VCCIO3_5_IOC_REG + 0x006c, __BITS(15,12) },
214 { RK3588_VCCIO3_5_IOC_REG + 0x0070, __BITS(3,0) },
215 { RK3588_VCCIO3_5_IOC_REG + 0x0070, __BITS(7,4) },
216 { RK3588_VCCIO3_5_IOC_REG + 0x0070, __BITS(11,8) },
217 { RK3588_VCCIO3_5_IOC_REG + 0x0070, __BITS(15,12) },
218 { RK3588_VCCIO3_5_IOC_REG + 0x0074, __BITS(3,0) },
219 { RK3588_VCCIO3_5_IOC_REG + 0x0074, __BITS(7,4) },
220 { RK3588_VCCIO3_5_IOC_REG + 0x0074, __BITS(11,8) },
221 { RK3588_VCCIO3_5_IOC_REG + 0x0074, __BITS(15,12) },
223 { RK3588_VCCIO3_5_IOC_REG + 0x0078, __BITS(3,0) },
224 { RK3588_VCCIO3_5_IOC_REG + 0x0078, __BITS(7,4) },
225 { RK3588_VCCIO3_5_IOC_REG + 0x0078, __BITS(11,8) },
226 { RK3588_VCCIO3_5_IOC_REG + 0x0078, __BITS(15,12) },
227 { RK3588_VCCIO3_5_IOC_REG + 0x007c, __BITS(3,0) },
228 { RK3588_VCCIO3_5_IOC_REG + 0x007c, __BITS(7,4) },
229 { RK3588_VCCIO3_5_IOC_REG + 0x007c, __BITS(11,8) },
230 { RK3588_VCCIO3_5_IOC_REG + 0x007c, __BITS(15,12) },
233 { RK3588_VCCIO6_IOC_REG + 0x0080, __BITS(3,0) },
234 { RK3588_VCCIO6_IOC_REG + 0x0080, __BITS(7,4) },
235 { RK3588_VCCIO6_IOC_REG + 0x0080, __BITS(11,8) },
236 { RK3588_VCCIO6_IOC_REG + 0x0080, __BITS(15,12) },
237 { RK3588_VCCIO6_IOC_REG + 0x0084, __BITS(3,0) },
238 { RK3588_VCCIO6_IOC_REG + 0x0084, __BITS(7,4) },
239 { RK3588_VCCIO6_IOC_REG + 0x0084, __BITS(11,8) },
240 { RK3588_VCCIO6_IOC_REG + 0x0084, __BITS(15,12) },
242 { RK3588_VCCIO6_IOC_REG + 0x0088, __BITS(3,0) },
243 { RK3588_VCCIO6_IOC_REG + 0x0088, __BITS(7,4) },
244 { RK3588_VCCIO6_IOC_REG + 0x0088, __BITS(11,8) },
245 { RK3588_VCCIO6_IOC_REG + 0x0088, __BITS(15,12) },
246 { RK3588_VCCIO6_IOC_REG + 0x008c, __BITS(3,0) },
247 { RK3588_VCCIO6_IOC_REG + 0x008c, __BITS(7,4) },
248 { RK3588_VCCIO6_IOC_REG + 0x008c, __BITS(11,8) },
249 { RK3588_VCCIO6_IOC_REG + 0x008c, __BITS(15,12) },
251 { RK3588_VCCIO6_IOC_REG + 0x0090, __BITS(3,0) },
252 { RK3588_VCCIO6_IOC_REG + 0x0090, __BITS(7,4) },
253 { RK3588_VCCIO3_5_IOC_REG + 0x0090, __BITS(11,8) },
254 { RK3588_VCCIO3_5_IOC_REG + 0x0090, __BITS(15,12) },
255 { RK3588_VCCIO3_5_IOC_REG + 0x0094, __BITS(3,0) },
256 { RK3588_VCCIO3_5_IOC_REG + 0x0094, __BITS(7,4) },
257 { RK3588_VCCIO3_5_IOC_REG + 0x0094, __BITS(11,8) },
258 { RK3588_VCCIO3_5_IOC_REG + 0x0094, __BITS(15,12) },
260 { RK3588_VCCIO2_IOC_REG + 0x0098, __BITS(3,0) },
261 { RK3588_VCCIO2_IOC_REG + 0x0098, __BITS(7,4) },
262 { RK3588_VCCIO2_IOC_REG + 0x0098, __BITS(11,8) },
263 { RK3588_VCCIO2_IOC_REG + 0x0098, __BITS(15,12) },
264 { RK3588_VCCIO2_IOC_REG + 0x009c, __BITS(3,0) },
265 { RK3588_VCCIO2_IOC_REG + 0x009c, __BITS(7,4) },
266 { RK3588_VCCIO2_IOC_REG + 0x009c, __BITS(11,8) },
267 { RK3588_VCCIO2_IOC_REG + 0x009c, __BITS(15,12) }
277 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(1,0) },
278 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(3,2) },
279 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(5,4) },
280 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(7,6) },
281 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(9,8) },
282 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(11,10) },
283 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(13,12) },
284 { RK3588_PMU1_IOC_REG + 0x0020, __BITS(15,14) },
286 { RK3588_PMU1_IOC_REG + 0x0024, __BITS(1,0) },
287 { RK3588_PMU1_IOC_REG + 0x0024, __BITS(3,2) },
288 { RK3588_PMU1_IOC_REG + 0x0024, __BITS(5,4) },
289 { RK3588_PMU1_IOC_REG + 0x0024, __BITS(7,6) },
290 { RK3588_PMU1_IOC_REG + 0x0024, __BITS(9,8) },
291 { RK3588_PMU2_IOC_REG + 0x0028, __BITS(11,10) },
292 { RK3588_PMU2_IOC_REG + 0x0028, __BITS(13,12) },
293 { RK3588_PMU2_IOC_REG + 0x0028, __BITS(15,14) },
295 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(1,0) },
296 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(3,2) },
297 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(5,4) },
298 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(7,6) },
299 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(9,8) },
300 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(11,10) },
301 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(13,12) },
302 { RK3588_PMU2_IOC_REG + 0x002c, __BITS(15,14) },
304 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(1,0) },
305 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(3,2) },
306 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(5,4) },
307 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(7,6) },
308 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(9,8) },
309 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(11,10) },
310 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(13,12) },
311 { RK3588_PMU2_IOC_REG + 0x0030, __BITS(15,14) },
314 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(1,0) },
315 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(3,2) },
316 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(5,4) },
317 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(7,6) },
318 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(9,8) },
319 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(11,10) },
320 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(13,12) },
321 { RK3588_VCCIO1_4_IOC_REG + 0x0110, __BITS(15,14) },
323 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(1,0) },
324 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(3,2) },
325 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(5,4) },
326 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(7,6) },
327 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(9,8) },
328 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(11,10) },
329 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(13,12) },
330 { RK3588_VCCIO1_4_IOC_REG + 0x0114, __BITS(15,14) },
332 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(1,0) },
333 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(3,2) },
334 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(5,4) },
335 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(7,6) },
336 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(9,8) },
337 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(11,10) },
338 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(13,12) },
339 { RK3588_VCCIO1_4_IOC_REG + 0x0118, __BITS(15,14) },
341 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(1,0) },
342 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(3,2) },
343 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(5,4) },
344 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(7,6) },
345 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(9,8) },
346 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(11,10) },
347 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(13,12) },
348 { RK3588_VCCIO1_4_IOC_REG + 0x011c, __BITS(15,14) },
351 { RK3588_EMMC_IOC_REG + 0x0120, __BITS(1,0) },
352 { RK3588_EMMC_IOC_REG + 0x0120, __BITS(3,2) },
353 { RK3588_EMMC_IOC_REG + 0x0120, __BITS(5,4) },
354 { RK3588_EMMC_IOC_REG + 0x0120, __BITS(7,6) },
355 { RK3588_EMMC_IOC_REG + 0x0120, __BITS(9,8) },
356 { RK3588_EMMC_IOC_REG + 0x0120, __BITS(11,10) },
357 { RK3588_VCCIO3_5_IOC_REG + 0x0120, __BITS(13,12) },
358 { RK3588_VCCIO3_5_IOC_REG + 0x0120, __BITS(15,14) },
360 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(1,0) },
361 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(3,2) },
362 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(5,4) },
363 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(7,6) },
364 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(9,8) },
365 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(11,10) },
366 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(13,12) },
367 { RK3588_VCCIO3_5_IOC_REG + 0x0124, __BITS(15,14) },
369 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(1,0) },
370 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(3,2) },
371 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(5,4) },
372 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(7,6) },
373 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(9,8) },
374 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(11,10) },
375 { RK3588_VCCIO3_5_IOC_REG + 0x0128, __BITS(13,12) },
376 __BITS(15,14) },
378 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(1,0) },
379 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(3,2) },
380 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(5,4) },
381 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(7,6) },
382 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(9,8) },
383 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(11,10) },
384 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(13,12) },
385 { RK3588_EMMC_IOC_REG + 0x012c, __BITS(15,14) },
388 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(1,0) },
389 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(3,2) },
390 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(5,4) },
391 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(7,6) },
392 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(9,8) },
393 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(11,10) },
394 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(13,12) },
395 { RK3588_VCCIO3_5_IOC_REG + 0x0130, __BITS(15,14) },
397 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(1,0) },
398 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(3,2) },
399 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(5,4) },
400 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(7,6) },
401 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(9,8) },
402 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(11,10) },
403 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(13,12) },
404 { RK3588_VCCIO3_5_IOC_REG + 0x0134, __BITS(15,14) },
406 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(1,0) },
407 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(3,2) },
408 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(5,4) },
409 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(7,6) },
410 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(9,8) },
411 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(11,10) },
412 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(13,12) },
413 { RK3588_VCCIO3_5_IOC_REG + 0x0138, __BITS(15,14) },
415 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(1,0) },
416 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(3,2) },
417 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(5,4) },
418 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(7,6) },
419 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(9,8) },
420 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(11,10) },
421 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(13,12) },
422 { RK3588_VCCIO3_5_IOC_REG + 0x013c, __BITS(15,14) },
425 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(1,0) },
426 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(3,2) },
427 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(5,4) },
428 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(7,6) },
429 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(9,8) },
430 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(11,10) },
431 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(13,12) },
432 { RK3588_VCCIO6_IOC_REG + 0x0140, __BITS(15,14) },
434 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(1,0) },
435 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(3,2) },
436 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(5,4) },
437 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(7,6) },
438 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(9,8) },
439 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(11,10) },
440 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(13,12) },
441 { RK3588_VCCIO6_IOC_REG + 0x0144, __BITS(15,14) },
443 { RK3588_VCCIO6_IOC_REG + 0x0148, __BITS(1,0) },
444 { RK3588_VCCIO6_IOC_REG + 0x0148, __BITS(3,2) },
445 { RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(5,4) },
446 { RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(7,6) },
447 { RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(9,8) },
448 { RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(11,10) },
449 { RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(13,12) },
450 { RK3588_VCCIO3_5_IOC_REG + 0x0148, __BITS(15,14) },
452 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(1,0) },
453 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(3,2) },
454 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(5,4) },
455 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(7,6) },
456 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(9,8) },
457 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(11,10) },
458 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(13,12) },
459 { RK3588_VCCIO2_IOC_REG + 0x014c, __BITS(15,14) }
653 { RK3588_PMU1_IOC_REG + 0x0000, __BITS(3,0) },
654 { RK3588_PMU1_IOC_REG + 0x0000, __BITS(7,4) },
655 { RK3588_PMU1_IOC_REG + 0x0000, __BITS(11,8) },
656 { RK3588_PMU1_IOC_REG + 0x0000, __BITS(15,12) },
657 { RK3588_PMU1_IOC_REG + 0x0004, __BITS(3,0) },
658 { RK3588_PMU1_IOC_REG + 0x0004, __BITS(7,4) },
659 { RK3588_PMU1_IOC_REG + 0x0004, __BITS(11,8) },
660 { RK3588_PMU1_IOC_REG + 0x0004, __BITS(15,12) },
662 { RK3588_PMU1_IOC_REG + 0x0008, __BITS(3,0) },
663 { RK3588_PMU1_IOC_REG + 0x0008, __BITS(7,4) },
664 { RK3588_PMU1_IOC_REG + 0x0008, __BITS(11,8) },
665 { RK3588_PMU1_IOC_REG + 0x0008, __BITS(15,12) },
666 { RK3588_BUS_IOC_REG + 0x000c, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x0000 },
667 { RK3588_BUS_IOC_REG + 0x000c, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x0000 },
668 { RK3588_BUS_IOC_REG + 0x000c, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x0000 },
669 { RK3588_BUS_IOC_REG + 0x000c, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x0000 },
671 { RK3588_BUS_IOC_REG + 0x0010, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x0004 },
672 { RK3588_BUS_IOC_REG + 0x0010, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x0004 },
673 { RK3588_BUS_IOC_REG + 0x0010, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x0004 },
674 { RK3588_BUS_IOC_REG + 0x0010, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x0004 },
675 { RK3588_BUS_IOC_REG + 0x0014, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x0008 },
676 { RK3588_BUS_IOC_REG + 0x0014, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x0008 },
677 { RK3588_BUS_IOC_REG + 0x0014, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x0008 },
678 { RK3588_BUS_IOC_REG + 0x0014, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x0008 },
680 { RK3588_BUS_IOC_REG + 0x0018, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x000c },
681 { RK3588_BUS_IOC_REG + 0x0018, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x000c },
682 { RK3588_BUS_IOC_REG + 0x0018, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x000c },
683 { RK3588_BUS_IOC_REG + 0x0018, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x000c },
684 { RK3588_BUS_IOC_REG + 0x001c, __BITS(3,0), RK3588_PMU2_IOC_REG + 0x0010 },
685 { RK3588_BUS_IOC_REG + 0x001c, __BITS(7,4), RK3588_PMU2_IOC_REG + 0x0010 },
686 { RK3588_BUS_IOC_REG + 0x001c, __BITS(11,8), RK3588_PMU2_IOC_REG + 0x0010 },
687 { RK3588_BUS_IOC_REG + 0x001c, __BITS(15,12), RK3588_PMU2_IOC_REG + 0x0010 },
690 { RK3588_BUS_IOC_REG + 0x0020, __BITS(3,0) },
691 { RK3588_BUS_IOC_REG + 0x0020, __BITS(7,4) },
692 { RK3588_BUS_IOC_REG + 0x0020, __BITS(11,8) },
693 { RK3588_BUS_IOC_REG + 0x0020, __BITS(15,12) },
694 { RK3588_BUS_IOC_REG + 0x0024, __BITS(3,0) },
695 { RK3588_BUS_IOC_REG + 0x0024, __BITS(7,4) },
696 { RK3588_BUS_IOC_REG + 0x0024, __BITS(11,8) },
697 { RK3588_BUS_IOC_REG + 0x0024, __BITS(15,12) },
699 { RK3588_BUS_IOC_REG + 0x0028, __BITS(3,0) },
700 { RK3588_BUS_IOC_REG + 0x0028, __BITS(7,4) },
701 { RK3588_BUS_IOC_REG + 0x0028, __BITS(11,8) },
702 { RK3588_BUS_IOC_REG + 0x0028, __BITS(15,12) },
703 { RK3588_BUS_IOC_REG + 0x002c, __BITS(3,0) },
704 { RK3588_BUS_IOC_REG + 0x002c, __BITS(7,4) },
705 { RK3588_BUS_IOC_REG + 0x002c, __BITS(11,8) },
706 { RK3588_BUS_IOC_REG + 0x002c, __BITS(15,12) },
708 { RK3588_BUS_IOC_REG + 0x0030, __BITS(3,0) },
709 { RK3588_BUS_IOC_REG + 0x0030, __BITS(7,4) },
710 { RK3588_BUS_IOC_REG + 0x0030, __BITS(11,8) },
711 { RK3588_BUS_IOC_REG + 0x0030, __BITS(15,12) },
712 { RK3588_BUS_IOC_REG + 0x0034, __BITS(3,0) },
713 { RK3588_BUS_IOC_REG + 0x0034, __BITS(7,4) },
714 { RK3588_BUS_IOC_REG + 0x0034, __BITS(11,8) },
715 { RK3588_BUS_IOC_REG + 0x0034, __BITS(15,12) },
717 { RK3588_BUS_IOC_REG + 0x0038, __BITS(3,0) },
718 { RK3588_BUS_IOC_REG + 0x0038, __BITS(7,4) },
719 { RK3588_BUS_IOC_REG + 0x0038, __BITS(11,8) },
720 { RK3588_BUS_IOC_REG + 0x0038, __BITS(15,12) },
721 { RK3588_BUS_IOC_REG + 0x003c, __BITS(3,0) },
722 { RK3588_BUS_IOC_REG + 0x003c, __BITS(7,4) },
723 { RK3588_BUS_IOC_REG + 0x003c, __BITS(11,8) },
724 { RK3588_BUS_IOC_REG + 0x003c, __BITS(15,12) },
727 { RK3588_BUS_IOC_REG + 0x0040, __BITS(3,0) },
728 { RK3588_BUS_IOC_REG + 0x0040, __BITS(7,4) },
729 { RK3588_BUS_IOC_REG + 0x0040, __BITS(11,8) },
730 { RK3588_BUS_IOC_REG + 0x0040, __BITS(15,12) },
731 { RK3588_BUS_IOC_REG + 0x0044, __BITS(3,0) },
732 { RK3588_BUS_IOC_REG + 0x0044, __BITS(7,4) },
733 { RK3588_BUS_IOC_REG + 0x0044, __BITS(11,8) },
734 { RK3588_BUS_IOC_REG + 0x0044, __BITS(15,12) },
736 { RK3588_BUS_IOC_REG + 0x0048, __BITS(3,0) },
737 { RK3588_BUS_IOC_REG + 0x0048, __BITS(7,4) },
738 { RK3588_BUS_IOC_REG + 0x0048, __BITS(11,8) },
739 { RK3588_BUS_IOC_REG + 0x0048, __BITS(15,12) },
740 { RK3588_BUS_IOC_REG + 0x004c, __BITS(3,0) },
741 { RK3588_BUS_IOC_REG + 0x004c, __BITS(7,4) },
742 { RK3588_BUS_IOC_REG + 0x004c, __BITS(11,8) },
743 { RK3588_BUS_IOC_REG + 0x004c, __BITS(15,12) },
745 { RK3588_BUS_IOC_REG + 0x0050, __BITS(3,0) },
746 { RK3588_BUS_IOC_REG + 0x0050, __BITS(7,4) },
747 { RK3588_BUS_IOC_REG + 0x0050, __BITS(11,8) },
748 { RK3588_BUS_IOC_REG + 0x0050, __BITS(15,12) },
749 { RK3588_BUS_IOC_REG + 0x0054, __BITS(3,0) },
750 { RK3588_BUS_IOC_REG + 0x0054, __BITS(7,4) },
751 { RK3588_BUS_IOC_REG + 0x0054, __BITS(11,8) },
752 { RK3588_BUS_IOC_REG + 0x0054, __BITS(15,12) },
754 { RK3588_BUS_IOC_REG + 0x0058, __BITS(3,0) },
755 { RK3588_BUS_IOC_REG + 0x0058, __BITS(7,4) },
756 { RK3588_BUS_IOC_REG + 0x0058, __BITS(11,8) },
757 { RK3588_BUS_IOC_REG + 0x0058, __BITS(15,12) },
758 { RK3588_BUS_IOC_REG + 0x005c, __BITS(3,0) },
759 { RK3588_BUS_IOC_REG + 0x005c, __BITS(7,4) },
760 { RK3588_BUS_IOC_REG + 0x005c, __BITS(11,8) },
761 { RK3588_BUS_IOC_REG + 0x005c, __BITS(15,12) },
764 { RK3588_BUS_IOC_REG + 0x0060, __BITS(3,0) },
765 { RK3588_BUS_IOC_REG + 0x0060, __BITS(7,4) },
766 { RK3588_BUS_IOC_REG + 0x0060, __BITS(11,8) },
767 { RK3588_BUS_IOC_REG + 0x0060, __BITS(15,12) },
768 { RK3588_BUS_IOC_REG + 0x0064, __BITS(3,0) },
769 { RK3588_BUS_IOC_REG + 0x0064, __BITS(7,4) },
770 { RK3588_BUS_IOC_REG + 0x0064, __BITS(11,8) },
771 { RK3588_BUS_IOC_REG + 0x0064, __BITS(15,12) },
773 { RK3588_BUS_IOC_REG + 0x0068, __BITS(3,0) },
774 { RK3588_BUS_IOC_REG + 0x0068, __BITS(7,4) },
775 { RK3588_BUS_IOC_REG + 0x0068, __BITS(11,8) },
776 { RK3588_BUS_IOC_REG + 0x0068, __BITS(15,12) },
777 { RK3588_BUS_IOC_REG + 0x006c, __BITS(3,0) },
778 { RK3588_BUS_IOC_REG + 0x006c, __BITS(7,4) },
779 { RK3588_BUS_IOC_REG + 0x006c, __BITS(11,8) },
780 { RK3588_BUS_IOC_REG + 0x006c, __BITS(15,12) },
782 { RK3588_BUS_IOC_REG + 0x0070, __BITS(3,0) },
783 { RK3588_BUS_IOC_REG + 0x0070, __BITS(7,4) },
784 { RK3588_BUS_IOC_REG + 0x0070, __BITS(11,8) },
785 { RK3588_BUS_IOC_REG + 0x0070, __BITS(15,12) },
786 { RK3588_BUS_IOC_REG + 0x0074, __BITS(3,0) },
787 { RK3588_BUS_IOC_REG + 0x0074, __BITS(7,4) },
788 { RK3588_BUS_IOC_REG + 0x0074, __BITS(11,8) },
789 { RK3588_BUS_IOC_REG + 0x0074, __BITS(15,12) },
791 { RK3588_BUS_IOC_REG + 0x0078, __BITS(3,0) },
792 { RK3588_BUS_IOC_REG + 0x0078, __BITS(7,4) },
793 { RK3588_BUS_IOC_REG + 0x0078, __BITS(11,8) },
794 { RK3588_BUS_IOC_REG + 0x0078, __BITS(15,12) },
795 { RK3588_BUS_IOC_REG + 0x007c, __BITS(3,0) },
796 { RK3588_BUS_IOC_REG + 0x007c, __BITS(7,4) },
797 { RK3588_BUS_IOC_REG + 0x007c, __BITS(11,8) },
798 { RK3588_BUS_IOC_REG + 0x007c, __BITS(15,12) },
801 { RK3588_BUS_IOC_REG + 0x0080, __BITS(3,0) },
802 { RK3588_BUS_IOC_REG + 0x0080, __BITS(7,4) },
803 { RK3588_BUS_IOC_REG + 0x0080, __BITS(11,8) },
804 { RK3588_BUS_IOC_REG + 0x0080, __BITS(15,12) },
805 { RK3588_BUS_IOC_REG + 0x0084, __BITS(3,0) },
806 { RK3588_BUS_IOC_REG + 0x0084, __BITS(7,4) },
807 { RK3588_BUS_IOC_REG + 0x0084, __BITS(11,8) },
808 { RK3588_BUS_IOC_REG + 0x0084, __BITS(15,12) },
810 { RK3588_BUS_IOC_REG + 0x0088, __BITS(3,0) },
811 { RK3588_BUS_IOC_REG + 0x0088, __BITS(7,4) },
812 { RK3588_BUS_IOC_REG + 0x0088, __BITS(11,8) },
813 { RK3588_BUS_IOC_REG + 0x0088, __BITS(15,12) },
814 { RK3588_BUS_IOC_REG + 0x008c, __BITS(3,0) },
815 { RK3588_BUS_IOC_REG + 0x008c, __BITS(7,4) },
816 { RK3588_BUS_IOC_REG + 0x008c, __BITS(11,8) },
817 { RK3588_BUS_IOC_REG + 0x008c, __BITS(15,12) },
819 { RK3588_BUS_IOC_REG + 0x0090, __BITS(3,0) },
820 { RK3588_BUS_IOC_REG + 0x0090, __BITS(7,4) },
821 { RK3588_BUS_IOC_REG + 0x0090, __BITS(11,8) },
822 { RK3588_BUS_IOC_REG + 0x0090, __BITS(15,12) },
823 { RK3588_BUS_IOC_REG + 0x0094, __BITS(3,0) },
824 { RK3588_BUS_IOC_REG + 0x0094, __BITS(7,4) },
825 { RK3588_BUS_IOC_REG + 0x0094, __BITS(11,8) },
826 { RK3588_BUS_IOC_REG + 0x0094, __BITS(15,12) },
828 { RK3588_BUS_IOC_REG + 0x0098, __BITS(3,0) },
829 { RK3588_BUS_IOC_REG + 0x0098, __BITS(7,4) },
830 { RK3588_BUS_IOC_REG + 0x0098, __BITS(11,8) },
831 { RK3588_BUS_IOC_REG + 0x0098, __BITS(15,12) },
832 { RK3588_BUS_IOC_REG + 0x009c, __BITS(3,0) },
833 { RK3588_BUS_IOC_REG + 0x009c, __BITS(7,4) },
834 { RK3588_BUS_IOC_REG + 0x009c, __BITS(11,8) },
835 { RK3588_BUS_IOC_REG + 0x009c, __BITS(15,12) }
Indexes created Sun Oct 19 02:09:48 GMT 2025