Cross Reference: /src/sys/arch/arm/rockchip/rk

Lines Matching refs:phandle
180 rk3588_eqos_clock_selection(struct rk_eqos_softc *rk_sc, int phandle)
185 	clock_in_out = fdtbus_get_string(phandle, "clock_in_out");
212 rk3588_eqos_get_unit(struct rk_eqos_softc *rk_sc, int phandle)
217 	fdtbus_get_reg(phandle, 0, &addr, &size);
236 rk_eqos_reset_gpio(const int phandle)
243 	if (!of_hasprop(phandle, "snps,reset-gpio"))
246 	pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio",
251 	reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len);
255 	reset_active_low = of_hasprop(phandle, "snps,reset-active-low");
268 rk_eqos_init_props(struct eqos_softc *sc, int phandle)
276 	if (of_hasprop(phandle, "snps,mixed-burst"))
278 	if (of_hasprop(phandle, "snps,tso"))
296 	const int phandle = faa->faa_phandle;
305 	    of_compatible_lookup(phandle, compat_data)->value;
309 		rk_sc->sc_id = ops->get_unit(rk_sc, phandle);
311 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
316 	rk_sc->sc_grf = fdtbus_syscon_acquire(phandle, "rockchip,grf");
321 	rk_sc->sc_php_grf = fdtbus_syscon_acquire(phandle, "rockchip,php_grf");
335 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
342 	fdtbus_clock_assign(phandle);
343 	for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) {
351 	for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) {
357 	if (rk_eqos_reset_gpio(phandle) != 0)
361 		ops->clock_selection(rk_sc, phandle);
363 	if (of_getprop_uint32(phandle, "tx_delay", &tx_delay) != 0)
365 	if (of_getprop_uint32(phandle, "rx_delay", &rx_delay) != 0)
368 	phy_mode = fdtbus_get_string(phandle, "phy-mode");
386 	rk_eqos_init_props(sc, phandle);
394 	if (fdtbus_intr_establish_xname(phandle, 0, IPL_NET, FDT_INTR_MPSAFE,
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