Lines Matching defs:HWRITE4
101 #define HWRITE4(sc, reg, val) \
104 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
106 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
306 HWRITE4(sc, PMA_CMN_CTRL1, 0x830);
308 HWRITE4(sc, XCVR_DIAG_LANE_FCM_EN_MGN(i), 0x90);
309 HWRITE4(sc, TX_RCVDET_EN_TMR(i), 0x960);
310 HWRITE4(sc, TX_RCVDET_ST_TMR(i), 0x30);
315 HWRITE4(sc, CMN_DIAG_HSCLK_SEL, reg);
318 HWRITE4(sc, CMN_PLL0_VCOCAL_INIT, 0xf0);
319 HWRITE4(sc, CMN_PLL0_VCOCAL_ITER, 0x18);
320 HWRITE4(sc, CMN_PLL0_INTDIV, 0xd0);
321 HWRITE4(sc, CMN_PLL0_FRACDIV, 0x4a4a);
322 HWRITE4(sc, CMN_PLL0_HIGH_THR, 0x34);
323 HWRITE4(sc, CMN_PLL0_SS_CTRL1, 0x1ee);
324 HWRITE4(sc, CMN_PLL0_SS_CTRL2, 0x7f03);
325 HWRITE4(sc, CMN_PLL0_DSM_DIAG, 0x20);
326 HWRITE4(sc, CMN_DIAG_PLL0_OVRD, 0);
327 HWRITE4(sc, CMN_DIAG_PLL0_FBH_OVRD, 0);
328 HWRITE4(sc, CMN_DIAG_PLL0_FBL_OVRD, 0);
329 HWRITE4(sc, CMN_DIAG_PLL0_V2I_TUNE, 0x7);
330 HWRITE4(sc, CMN_DIAG_PLL0_CP_TUNE, 0x45);
331 HWRITE4(sc, CMN_DIAG_PLL0_LF_PROG, 0x8);
334 HWRITE4(sc, TX_PSC_A0(0), 0x7799);
335 HWRITE4(sc, TX_PSC_A1(0), 0x7798);
336 HWRITE4(sc, TX_PSC_A2(0), 0x5098);
337 HWRITE4(sc, TX_PSC_A3(0), 0x5098);
338 HWRITE4(sc, TX_TXCC_MGNFS_MULT_000(0), 0x0);
339 HWRITE4(sc, XCVR_DIAG_BIDI_CTRL(0), 0xbf);
341 HWRITE4(sc, RX_PSC_A0(1), 0xa6fd);
342 HWRITE4(sc, RX_PSC_A1(1), 0xa6fd);
343 HWRITE4(sc, RX_PSC_A2(1), 0xa410);
344 HWRITE4(sc, RX_PSC_A3(1), 0x2410);
345 HWRITE4(sc, RX_PSC_CAL(1), 0x23ff);
346 HWRITE4(sc, RX_SIGDET_HL_FILT_TMR(1), 0x13);
347 HWRITE4(sc, RX_REE_CTRL_DATA_MASK(1), 0x03e7);
348 HWRITE4(sc, RX_DIAG_SIGDET_TUNE(1), 0x1004);
349 HWRITE4(sc, RX_PSC_RDY(1), 0x2010);
350 HWRITE4(sc, XCVR_DIAG_BIDI_CTRL(1), 0xfb);
352 HWRITE4(sc, PMA_LANE_CFG, PIN_ASSIGN_D_F);
354 HWRITE4(sc, DP_MODE_CTL, DP_MODE_ENTER_A2);
Indexes created Tue Sep 30 20:09:53 GMT 2025