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Lines Matching refs:WR4

186 #define	WR4(sc, reg, val)			\
194 	WR4(sc, reg, ((uint32_t)mask << 16) | val);
248 	WR4(sc, VOP_DSP_CTRL1, val);
258 	WR4(sc, VOP_SYS_CTRL, val);
325 	WR4(sc, VOP_WIN0_ACT_INFO, val);
331 	WR4(sc, VOP_WIN0_DSP_INFO, val);
339 	WR4(sc, VOP_WIN0_DSP_ST, val);
341 	WR4(sc, VOP_WIN0_COLOR_KEY, 0);
354 	WR4(sc, VOP_WIN0_CTRL, val);
374 	WR4(sc, VOP_WIN0_VIR, val);
377 	WR4(sc, VOP_WIN0_YRGB_MST, (uint32_t)paddr);
387 	WR4(sc, VOP_WIN0_CTRL, 0);	/* clear WIN0_EN */
437 	WR4(sc, VOP_SYS_CTRL, val);
440 	WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN);
519 	WR4(sc, VOP_SYS_CTRL, val);
524 	WR4(sc, VOP_DSP_CTRL0, val);
528 	WR4(sc, VOP_POST_DSP_HACT_INFO, val);
532 	WR4(sc, VOP_DSP_HACT_ST_END, val);
536 	WR4(sc, VOP_DSP_HTOTAL_HS_END, val);
540 	WR4(sc, VOP_POST_DSP_VACT_INFO, val);
544 	WR4(sc, VOP_DSP_VACT_ST_END, val);
548 	WR4(sc, VOP_DSP_VTOTAL_VS_END, val);
564 	WR4(sc, VOP_SYS_CTRL, val);
583 	WR4(sc, VOP_REG_CFG_DONE, REG_LOAD_EN);